QSPC_SMID_ENTRY1 (CPM5_DMA_CSR) Register Description
| Register Name | QSPC_SMID_ENTRY1 |
|---|---|
| Offset Address | 0x0000001004 |
| Absolute Address |
0x00FCE21004 (CPM5_DMA0_CSR) 0x00FCEA1004 (CPM5_DMA1_CSR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register space to store SMID values for Queue Space transactions to map SMID->Host ID. Each register stores 1 SMID each for H2C, C2H, and C2H WRB transactions, for a total of 16 registers and 16 SMIDs per type of queue space register. SMIDs for INT transactions are stored in QSPC_SMID_INT registers. |
QSPC_SMID_ENTRY1 (CPM5_DMA_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:30 | razRead as zero | 0x0 | Reserved |
| smid_h2c | 29:20 | rwNormal read/write | 0x0 | CAM Entry for H2C SMID value |
| smid_c2h | 19:10 | rwNormal read/write | 0x0 | CAM Entry for C2H SMID value |
| smid_c2h_wrb | 9:0 | rwNormal read/write | 0x0 | CAM Entry for C2H WRB SMID value |