PM_L1_REENTRY_DELAY (CPM4_PCIE1_ATTR) Register Description
| Register Name | PM_L1_REENTRY_DELAY |
|---|
| Offset Address | 0x00000000D8 |
|---|
| Absolute Address |
0x00FCA600D8 (CPM4_PCIE1_ATTR)
|
|---|
| Width | 32 |
|---|
| Type | rwNormal read/write |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | L1 State Re-entry Delay Register: Time (in units of 4 ns) the core will wait before it re-enters the L1 state if its link partner transitions the link to L0 while all the Functions of the core are in D3 power state. The core will change the power state of the link from L0 to L1 if no activity is detected both on the transmit and receive sides before this interval, while all Function are in D3 state and the link is in L0. Setting this register to 0 disables re-rentry to L1 state if the link partner returns the link to L0 from L1 when all the Functions of the core are in D3 state. This register control only the re-entry to L1. This register control only the re-entry to L1. The initial transition to L1 always occurs when the all the Functions of the core are set to the D3 state. The defaults are nominal values that should not be changed. |
|---|
This register should only be written to during reset of the PCIe block
PM_L1_REENTRY_DELAY (CPM4_PCIE1_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| attr | 31:0 | rwNormal read/write | 0x0 | |