PM_ENABLE_L23_ENTRY (CPM5_PCIE_ATTR) Register Description
| Register Name | PM_ENABLE_L23_ENTRY |
|---|---|
| Offset Address | 0x0000001320 |
| Absolute Address |
0x00FCE09320 (CPM5_PCIE0_ATTR) 0x00FCE89320 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Root Port Enter L23 Enable: When set to FALSE, Block will not transition the Physical link state to L2/L3 when its link partner enters the L23_Ready power management state. When (optionally) set to TRUE, the Blockwill transition Physical link state to L2/L3 Idle when the link partner enters L23_Ready. Once the Block enters L2/L3 Idle, a reset is needed to transition it out of L2/L3 Idle. |
This register should only be written to during reset of the PCIe block
PM_ENABLE_L23_ENTRY (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 |