PM_ASPML0S_TIMEOUT (CPM4_PCIE0_ATTR) Register Description
| Register Name | PM_ASPML0S_TIMEOUT |
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| Offset Address | 0x00000000D4 |
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| Absolute Address |
0x00FCA500D4 (CPM4_PCIE0_ATTR)
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| Width | 32 |
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| Type | rwNormal read/write |
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| Reset Value | 0x00000000 |
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| Description | L0S Timeout Limit Register: Timeout value for transitioning to the L0S power state. If the transmit side has been idle for this interval, the core will transmit the idle sequence on the link and transition the state of the link to L0S. Contains the timeout value (in units of4 ns) for transitioning to the L0S power state Setting it to 0 permanently disables the transition to the L0S power state. |
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This register should only be written to during reset of the PCIe block
PM_ASPML0S_TIMEOUT (CPM4_PCIE0_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| attr | 15:0 | rwNormal read/write | 0x0 | |