PL_SRIS_SKPOS_GEN_SPD_VEC (CPM4_PCIE0_ATTR) Register Description
| Register Name | PL_SRIS_SKPOS_GEN_SPD_VEC |
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| Offset Address | 0x00000001E4 |
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| Absolute Address |
0x00FCA501E4 (CPM4_PCIE0_ATTR)
|
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| Width | 32 |
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| Type | rwNormal read/write |
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| Reset Value | 0x00000000 |
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| Description | Link Capabilities 2 Register: : Lower SKP OS Generation Supported Speeds Vector Used by PL when SRIS is enabled. |
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This register should only be written to during reset of the PCIe block
PL_SRIS_SKPOS_GEN_SPD_VEC (CPM4_PCIE0_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| attr | 6:0 | rwNormal read/write | 0x0 | attr |