PL_RCVLCK_DISABLE_USP_EXTN_SYNC_CHECK (CPM5_PCIE_ATTR) Register Description
| Register Name | PL_RCVLCK_DISABLE_USP_EXTN_SYNC_CHECK |
|---|---|
| Offset Address | 0x0000000388 |
| Absolute Address |
0x00FCE08388 (CPM5_PCIE0_ATTR) 0x00FCE88388 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Chicken bit, enables EXTN sync check for USP when set:0 |
This register should only be written to during reset of the PCIe block
PL_RCVLCK_DISABLE_USP_EXTN_SYNC_CHECK (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 |