PL_N_FTS (CPM4_PCIE0_ATTR) Register Description
| Register Name | PL_N_FTS |
|---|
| Offset Address | 0x00000000FC |
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| Absolute Address |
0x00FCA500FC (CPM4_PCIE0_ATTR)
|
|---|
| Width | 32 |
|---|
| Type | rwNormal read/write |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | Sets the number of FTS OS, advertised in the TS1 Ordered Sets. Value supported by Xilinx GTs is 255. |
|---|
This register should only be written to during reset of the PCIe block
PL_N_FTS (CPM4_PCIE0_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| attr | 7:0 | rwNormal read/write | 0x0 | attr |