PL_LANE5_EQ_CONTROL (CPM4_PCIE0_ATTR) Register Description
| Register Name | PL_LANE5_EQ_CONTROL |
|---|---|
| Offset Address | 0x000000012C |
| Absolute Address | 0x00FCA5012C (CPM4_PCIE0_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Lane#5 Equalization Control Register: Sets the appropriate lane specific entry in the Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint. Lower 16b for Gen3 operation and Upper 16b for Gen4 operation.Bits 7, 15, 23, 31 are unused. |
This register should only be written to during reset of the PCIe block
PL_LANE5_EQ_CONTROL (CPM4_PCIE0_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 31:0 | rwNormal read/write | 0x0 |