PL_EQ_TX_POSTCUR_C (CPM4_PCIE1_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

PL_EQ_TX_POSTCUR_C (CPM4_PCIE1_ATTR) Register Description

Register NamePL_EQ_TX_POSTCUR_C
Offset Address0x0000000270
Absolute Address 0x00FCA60270 (CPM4_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTx POST-Cursor for PresetC

This register should only be written to during reset of the PCIe block

PL_EQ_TX_POSTCUR_C (CPM4_PCIE1_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 5:0rwNormal read/write0x0