PL_EQ_SHORT_ADAPT_PHASE (CPM5_PCIE_ATTR) Register Description
| Register Name | PL_EQ_SHORT_ADAPT_PHASE |
|---|---|
| Offset Address | 0x0000000198 |
| Absolute Address |
0x00FCE08198 (CPM5_PCIE0_ATTR) 0x00FCE88198 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Shorten the Receive Adaptation Phase: When set to TRUE, EQ Phase-2 for EP and Phase-3 for RP will return the received Tx Preset OR Coefficients as the the new proposed settings. Anticipate use for simulation speed-up and debug purposes. |
This register should only be written to during reset of the PCIe block
PL_EQ_SHORT_ADAPT_PHASE (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 |