PL_EQ_DEFAULT_CCIX_EDR_TX_PRESET (CPM5_PCIE_ATTR) Register Description
| Register Name | PL_EQ_DEFAULT_CCIX_EDR_TX_PRESET |
|---|---|
| Offset Address | 0x0000000348 |
| Absolute Address |
0x00FCE08348 (CPM5_PCIE0_ATTR) 0x00FCE88348 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Default CCIX EDR Tx Preset: This value is used in transmitted TS1s by Endpoint in EQ Phase0,if no EQ TS2 are receied during EQ Phase0. bits[3:0] are for 20G operation, bits[7:4] are for 25G operation. Others bits are reserved. |
This register should only be written to during reset of the PCIe block
PL_EQ_DEFAULT_CCIX_EDR_TX_PRESET (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 15:0 | rwNormal read/write | 0x0 |