PL_EQ_ADAPT_DISABLE_COEFF_CHECK (CPM4_PCIE0_ATTR) Register Description
| Register Name | PL_EQ_ADAPT_DISABLE_COEFF_CHECK |
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| Offset Address | 0x0000000168 |
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| Absolute Address |
0x00FCA50168 (CPM4_PCIE0_ATTR)
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| Width | 32 |
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| Type | rwNormal read/write |
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| Reset Value | 0x00000000 |
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| Description | Disable checks on Received Coefficients: When set to TRUE, received coefficient cheking is disabled (no rejection) during EQ Phase-3 for EP and EQ Phase-2 for RP. Bit0 if for Gen3 operation, Bit1 is for Gen4 operation. |
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This register should only be written to during reset of the PCIe block
PL_EQ_ADAPT_DISABLE_COEFF_CHECK (CPM4_PCIE0_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| attr | 1:0 | rwNormal read/write | 0x0 | |