PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE (CPM5_PCIE_ATTR) Register Description
| Register Name | PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE |
|---|---|
| Offset Address | 0x000000022C |
| Absolute Address |
0x00FCE0822C (CPM5_PCIE0_ATTR) 0x00FCE8822C (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Control SKP OS Parity and CRC Check Disable: |
This register should only be written to during reset of the PCIe block
PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 |