PFx_SRIOV_SUPPORTED_PAGE_SIZE_12 (CPM5_PCIE_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

PFx_SRIOV_SUPPORTED_PAGE_SIZE_12 (CPM5_PCIE_ATTR) Register Description

Register NamePFx_SRIOV_SUPPORTED_PAGE_SIZE_12
Offset Address0x000000173C
Absolute Address 0x00FCE0973C (CPM5_PCIE0_ATTR)
0x00FCE8973C (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPage Size Supported By Device: This field indicates the page sizes supported by the PF. This PF supports a page size of 2n+12 if bit n is Set

This register should only be written to during reset of the PCIe block

PFx_SRIOV_SUPPORTED_PAGE_SIZE_12 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x0