PFx_SRIOV_SUPPORTED_PAGE_SIZE_1 (CPM5_PCIE_ATTR) Register Description
| Register Name | PFx_SRIOV_SUPPORTED_PAGE_SIZE_1 |
|---|---|
| Offset Address | 0x0000001710 |
| Absolute Address |
0x00FCE09710 (CPM5_PCIE0_ATTR) 0x00FCE89710 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Page Size Supported By Device: This field indicates the page sizes supported by the PF. This PF supports a page size of 2n+12 if bit n is Set |
This register should only be written to during reset of the PCIe block
PFx_SRIOV_SUPPORTED_PAGE_SIZE_1 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 31:0 | rwNormal read/write | 0x0 |