PFx_SRIOV_FIRST_VF_OFFSET_6 (CPM5_PCIE_ATTR) Register Description
| Register Name | PFx_SRIOV_FIRST_VF_OFFSET_6 |
|---|---|
| Offset Address | 0x00000016A0 |
| Absolute Address |
0x00FCE096A0 (CPM5_PCIE0_ATTR) 0x00FCE896A0 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Offset of First VF: Allowed values for the first SR-IOV PF are: 16D. For all subsequent SR-IOV enabled PFs value allowed is sum (PFx_SRIOV_CAP_TOTAL_VF + PFx_SRIOV_FIRST_VF_OFFSET -1) taken for the preious SR-IOV PF. 0h if the PF does not support SR-IOV. |
This register should only be written to during reset of the PCIe block
PFx_SRIOV_FIRST_VF_OFFSET_6 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 15:0 | rwNormal read/write | 0x0 |