PFx_SRIOV_CAP_VER_1 (CPM4_PCIE0_ATTR) Register Description
| Register Name | PFx_SRIOV_CAP_VER_1 |
|---|
| Offset Address | 0x00000007E8 |
|---|
| Absolute Address |
0x00FCA507E8 (CPM4_PCIE0_ATTR)
|
|---|
| Width | 32 |
|---|
| Type | rwNormal read/write |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | SRIOV Capability Version: Bits 19:16 SRIOV Extended Capability Header Register |
|---|
This register should only be written to during reset of the PCIe block
PFx_SRIOV_CAP_VER_1 (CPM4_PCIE0_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| attr | 3:0 | rwNormal read/write | 0x0 | |