PFx_SRIOV_CAP_INITIAL_VF_2 (CPM4_PCIE0_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

PFx_SRIOV_CAP_INITIAL_VF_2 (CPM4_PCIE0_ATTR) Register Description

Register NamePFx_SRIOV_CAP_INITIAL_VF_2
Offset Address0x000000080C
Absolute Address 0x00FCA5080C (CPM4_PCIE0_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionInitial Number of VFs: Initial number of VFs configured for PF0.

This register should only be written to during reset of the PCIe block

PFx_SRIOV_CAP_INITIAL_VF_2 (CPM4_PCIE0_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr15:0rwNormal read/write0x0