PFx_SRIOV_BAR0_CONTROL_3 (CPM5_PCIE_ATTR) Register Description
| Register Name | PFx_SRIOV_BAR0_CONTROL_3 |
|---|---|
| Offset Address | 0x0000001758 |
| Absolute Address |
0x00FCE09758 (CPM5_PCIE0_ATTR) 0x00FCE89758 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | VF BAR0 Control - Specifies the configuration of BAR 0. The various encodings are: 000: Disabled 001-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable 110: Part of 64-bit memory BAR 0-1, non-prefetchable 111: Part of 64-bit memory BAR 0-1, prefetchable |
This register should only be written to during reset of the PCIe block
PFx_SRIOV_BAR0_CONTROL_3 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 2:0 | rwNormal read/write | 0x0 |