PFx_REVISION_ID_0 (CPM5_PCIE_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

PFx_REVISION_ID_0 (CPM5_PCIE_ATTR) Register Description

Register NamePFx_REVISION_ID_0
Offset Address0x00000007E0
Absolute Address 0x00FCE087E0 (CPM5_PCIE0_ATTR)
0x00FCE887E0 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionRevision ID: Per Function Revsion ID

This register should only be written to during reset of the PCIe block

PFx_REVISION_ID_0 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 7:0rwNormal read/write0x0