PFx_DEV_CAP_MAX_PAYLOAD_SIZE_8 (CPM5_PCIE_ATTR) Register Description
| Register Name | PFx_DEV_CAP_MAX_PAYLOAD_SIZE_8 |
|---|---|
| Offset Address | 0x0000000DB4 |
| Absolute Address |
0x00FCE08DB4 (CPM5_PCIE0_ATTR) 0x00FCE88DB4 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Capability Max Payload Size. This field indicates the maximum payload size that the Function can support for TLPs. Defined encodings are: 000b - 128 bytes max payload size 001b - 256 bytes max payload size 010b - 512 bytes max payload size 011b - 1024 bytes max payload size |
This register should only be written to during reset of the PCIe block
PFx_DEV_CAP_MAX_PAYLOAD_SIZE_8 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 2:0 | rwNormal read/write | 0x0 |