PFx_BAR5_CONTROL_14 (CPM5_PCIE_ATTR) Register Description
| Register Name | PFx_BAR5_CONTROL_14 |
|---|---|
| Offset Address | 0x0000000C4C |
| Absolute Address |
0x00FCE08C4C (CPM5_PCIE0_ATTR) 0x00FCE88C4C (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | BAR5 Control - Specifies the configuration of BAR 5. The Endpoint, the various encodings are: 000: Disabled 001: 32-bit IO BAR 010-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable For non-Endpoint (Type 1) Config Space, the Prefetchable Memory Base & Limit encodings are: 000: Disabled 001: 32-bit Enabled 011: 64-bit Enabled 010,100-111: Reserved NOTE: For non-Endpoint (Type 1) Config Space, BAR 5 Aperture must be programmed to 0. |
This register should only be written to during reset of the PCIe block
PFx_BAR5_CONTROL_14 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 2:0 | rwNormal read/write | 0x0 |