PF1_Wr_Cache (CPM4_DMA_ATTR) Register Description
| Register Name | PF1_Wr_Cache |
|---|---|
| Offset Address | 0x0000000850 |
| Absolute Address | 0x00FCA70850 (CPM4_DMA_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | multiq AIXMM_AWCACHE setting |
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_pf1_wr_cache
PF1_Wr_Cache (CPM4_DMA_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 3:0 | rwNormal read/write | 0x0 |