PF1_CCIX_PDVSEC_PCSR_SIZE (CPM5_PCIE_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2025-09-25
Revision
1.5

PF1_CCIX_PDVSEC_PCSR_SIZE (CPM5_PCIE_ATTR) Register Description

Register NamePF1_CCIX_PDVSEC_PCSR_SIZE
Offset Address0x0000001E58
Absolute Address 0x00FCE09E58 (CPM5_PCIE0_ATTR)
0x00FCE89E58 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPF1 CCIX Protocol DVSEC CSR Region Size

This register should only be written to during reset of the PCIe block

PF1_CCIX_PDVSEC_PCSR_SIZE (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr11:0rwNormal read/write0x0