PF0_MARGINING_CAP_VER (CPM4_PCIE0_ATTR) Register Description
| Register Name | PF0_MARGINING_CAP_VER |
|---|---|
| Offset Address | 0x0000000AD0 |
| Absolute Address | 0x00FCA50AD0 (CPM4_PCIE0_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Margining Cap Version |
This register should only be written to during reset of the PCIe block
PF0_MARGINING_CAP_VER (CPM4_PCIE0_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 3:0 | rwNormal read/write | 0x0 |