PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN5 (CPM5_PCIE_ATTR) Register Description
| Register Name | PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN5 |
|---|---|
| Offset Address | 0x0000000E14 |
| Absolute Address |
0x00FCE08E14 (CPM5_PCIE0_ATTR) 0x00FCE88E14 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Sets the exit latency from L0s state to be applied (at 32G) where separate clocks are used. Transferred to the Link Capabilities register. |
This register should only be written to during reset of the PCIe block
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN5 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 2:0 | rwNormal read/write | 0x0 |