PF0_CCIX_PDVSEC_PCR_SIZE (CPM4_PCIE1_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

PF0_CCIX_PDVSEC_PCR_SIZE (CPM4_PCIE1_ATTR) Register Description

Register NamePF0_CCIX_PDVSEC_PCR_SIZE
Offset Address0x0000000A74
Absolute Address 0x00FCA60A74 (CPM4_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPF0 CCIX Protocol DVSEC CR Region Size

This register should only be written to during reset of the PCIe block

PF0_CCIX_PDVSEC_PCR_SIZE (CPM4_PCIE1_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr11:0rwNormal read/write0x0