PF0_CCIX_PDVSEC_CAP_NEXTPTR (CPM5_PCIE_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2025-09-25
Revision
1.5

PF0_CCIX_PDVSEC_CAP_NEXTPTR (CPM5_PCIE_ATTR) Register Description

Register NamePF0_CCIX_PDVSEC_CAP_NEXTPTR
Offset Address0x0000001E1C
Absolute Address 0x00FCE09E1C (CPM5_PCIE0_ATTR)
0x00FCE89E1C (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPF0 CCIX Protocol DVSEC Next Pointer

This register should only be written to during reset of the PCIe block

PF0_CCIX_PDVSEC_CAP_NEXTPTR (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr11:0rwNormal read/write0x0