PCIeBar2AXIBar_5_Wr_Sec_PF0_VF (CPM4_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

PCIeBar2AXIBar_5_Wr_Sec_PF0_VF (CPM4_DMA_ATTR) Register Description

Register NamePCIeBar2AXIBar_5_Wr_Sec_PF0_VF
Offset Address0x0000000570
Absolute Address 0x00FCA70570 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionARPROT value for PF0 VF BAR5 writes

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_pciebar2axibar_5_wr_sec_pf0_vf

PCIeBar2AXIBar_5_Wr_Sec_PF0_VF (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0