PCIeBar2AXIBar_3_Rd_Cache_PF3 (CPM4_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

PCIeBar2AXIBar_3_Rd_Cache_PF3 (CPM4_DMA_ATTR) Register Description

Register NamePCIeBar2AXIBar_3_Rd_Cache_PF3
Offset Address0x0000000488
Absolute Address 0x00FCA70488 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionARCACHE value for PF3 BAR3 reads

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_pciebar2axibar_3_rd_cache_pf3

PCIeBar2AXIBar_3_Rd_Cache_PF3 (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 3:0rwNormal read/write0x0