PCIeBar2AXIBar_3_PF3_H (CPM4_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2025-09-25
Revision
1.5

PCIeBar2AXIBar_3_PF3_H (CPM4_DMA_ATTR) Register Description

Register NamePCIeBar2AXIBar_3_PF3_H
Offset Address0x0000000444
Absolute Address 0x00FCA70444 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionBits[63:12] Bar Translation for PF3 BAR3

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_pciebar2axibar_3_pf3_h

PCIeBar2AXIBar_3_PF3_H (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x0