PCIeBar2AXIBar_2_Wr_Cache_PF0 (CPM4_DMA_ATTR) Register Description
| Register Name | PCIeBar2AXIBar_2_Wr_Cache_PF0 |
|---|
| Offset Address | 0x0000000270 |
|---|
| Absolute Address |
0x00FCA70270 (CPM4_DMA_ATTR)
|
|---|
| Width | 32 |
|---|
| Type | rwNormal read/write |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | ARCACHE value for PF0 BAR2 writes |
|---|
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_pciebar2axibar_2_wr_cache_pf0
PCIeBar2AXIBar_2_Wr_Cache_PF0 (CPM4_DMA_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| attr | 3:0 | rwNormal read/write | 0x0 | Write cache attribute for PF0 PCIe BAR 2 AXI transactions. |