PCIeBar2AXIBar_0_PF3_H (CPM4_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

PCIeBar2AXIBar_0_PF3_H (CPM4_DMA_ATTR) Register Description

Register NamePCIeBar2AXIBar_0_PF3_H
Offset Address0x000000042C
Absolute Address 0x00FCA7042C (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionBits[63:12] Bar Translation for PF3 BAR0

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_pciebar2axibar_0_pf3_h

PCIeBar2AXIBar_0_PF3_H (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x0