H2C2_CHANNEL_PERFORMANCE_CYCLE_COUNT1 (CPM4_XDMA_CSR) Register Description
| Register Name | H2C2_CHANNEL_PERFORMANCE_CYCLE_COUNT1 |
|---|---|
| Offset Address | 0x00000002C8 |
| Absolute Address | 0x00E10002C8 (CPM4_XDMA_CSR) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | H2C2_CHANNEL_PERFORMANCE_CYCLE_COUNT1 |
H2C2_CHANNEL_PERFORMANCE_CYCLE_COUNT1 (CPM4_XDMA_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:17 | roRead-only | 0x0 | reserved |
| pmon_cyc_count_maxed | 16 | roRead-only | 0x0 | Cycle count maximum was hit. |
| Reserved | 15:10 | roRead-only | 0x0 | reserved |
| pmon_cyc_count | 9:0 | roRead-only | 0x0 | pmon_cyc_count[41:32]. Increments once per clock while running. See PerformanceControl.Clear and PerformanceControl.Auto for clearing. |