H2C1_CHANNEL_CONTROL_WTC (CPM4_XDMA_CSR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID: AM012
Release Date: 2024-08-19
Revision: 1.4

H2C1_CHANNEL_CONTROL_WTC (CPM4_XDMA_CSR) Register Description

Register Name	H2C1_CHANNEL_CONTROL_WTC
Offset Address	0x000000010C
Absolute Address	0x00E100010C (CPM4_XDMA_CSR)
Width	32
Type	wtcReadable, write a 1 to clear
Reset Value	0x00000000
Description	H2C1_CHANNEL_CONTROL_WTC

H2C1_CHANNEL_CONTROL_WTC (CPM4_XDMA_CSR) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	31:27	wtcReadable, write a 1 to clear	0x0	reserved
pollmode_wb_enable	26	wtcReadable, write a 1 to clear	0x0	Poll mode writeback enable. When this bit is set the DMA writes back the completed descriptor count when a descriptor with the Completed bit set, is completed.
non_inc_mode	25	wtcReadable, write a 1 to clear	0x0	Non-incrementing address mode is not supported. This field should always be zero.
ie_linkdown	24	wtcReadable, write a 1 to clear	0x0	Set to 1 to enable logging of Status.Linkdown
ie_desc_error	23:19	wtcReadable, write a 1 to clear	0x0	Set to all 1s (0x1F) to enable logging of Status.Desc_error and to stop the engine if the error is detected.
ie_write_error	18:14	wtcReadable, write a 1 to clear	0x0	Set to all 1s (0x1F) to enable logging of Status.Write_error and to stop the engine if the error is detected.
ie_read_error	13:9	wtcReadable, write a 1 to clear	0x0	Set to all 1s (0x1F) to enable logging of Status.Read_error and to stop the engine if the error is detected.
Reserved	8:7	wtcReadable, write a 1 to clear	0x0	reserved
ie_idle_stopped	6	wtcReadable, write a 1 to clear	0x0	Set to 1 to enable logging of Status.Idle_stopped
ie_invalid_length	5	wtcReadable, write a 1 to clear	0x0	Set to 1 to enable logging of Status.Invalid_length
ie_magic_stopped	4	wtcReadable, write a 1 to clear	0x0	Set to 1 to enable logging of Status.Magic_stopped
ie_align_mismatch	3	wtcReadable, write a 1 to clear	0x0	Set to 1 to enable logging of Status.Align_mismatch
ie_descriptor_completed	2	wtcReadable, write a 1 to clear	0x0	Set to 1 to enable logging of Status.Descriptor_completed
ie_descriptor_stopped	1	wtcReadable, write a 1 to clear	0x0	Set to 1 to enable logging of Status.Descriptor_stopped
run	0	wtcReadable, write a 1 to clear	0x0	Set to 1 to start the SGDMA engine. Reset to 0 to stop it; if it is busy it completes the current descriptor.