GT_EQ_POST_CUR18 (CPM5_PCIE_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

GT_EQ_POST_CUR18 (CPM5_PCIE_ATTR) Register Description

Register NameGT_EQ_POST_CUR18
Offset Address0x00000004AC
Absolute Address 0x00FCE084AC (CPM5_PCIE0_ATTR)
0x00FCE884AC (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMap to post cursor 18

This register should only be written to during reset of the PCIe block

GT_EQ_POST_CUR18 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 4:0rwNormal read/write0x0