GICH_MISR (APU_GIC_A72_VIFCTL) Register Description
| Register Name | GICH_MISR |
|---|---|
| Offset Address | 0x0000000010 |
| Absolute Address | 0x00F9050010 (APU_GIC_VIFCTL) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | GICH_MISR |
GICH_MISR (APU_GIC_A72_VIFCTL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| VGrp1D | 7 | roRead-only | 0 | |
| VGrp1E | 6 | roRead-only | 0 | |
| VGrp0D | 5 | roRead-only | 0 | |
| VGrp0E | 4 | roRead-only | 0 | |
| NP | 3 | roRead-only | 0 | |
| LRENP | 2 | roRead-only | 0 | |
| U | 1 | roRead-only | 0 | |
| EOI | 0 | roRead-only | 0 |