CPM5_DBG_REF_CTRL (CPM5_CRX) Register Description
| Register Name | CPM5_DBG_REF_CTRL |
|---|---|
| Offset Address | 0x0000000108 |
| Absolute Address | 0x00FCDC0108 (CPM5_CRX) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x02002500 |
| Description | Enable and Divider controls for cpm_dbg_clk. All SOC Debug features run on this clock |
CPM5_DBG_REF_CTRL (CPM5_CRX) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | roRead-only | 0x0 | This field is reserved |
| CLKACT | 25 | rwNormal read/write | 0x1 | Clock active signal. 0 = disable the clock. 1 = enable the clock. |
| Reserved | 24:18 | roRead-only | 0x0 | This field is reserved |
| DIVISOR0 | 17:8 | rwNormal read/write | 0x25 | 10 bit divider |
| Reserved | 7:3 | roRead-only | 0x0 | This field is reserved |
| Reserved | 2:0 | roRead-only | 0x0 | This field is reserved |