CPM4_PCIE1_ATTR Module - AM012

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2024-08-19
Revision
1.4

CPM4_PCIE1_ATTR Module Description

Module NameCPM4_PCIE1_ATTR Module
Modules of this TypeCPM4_PCIE1_ATTR
Base Addresses 0x00FCA60000 (CPM4_PCIE1_ATTR)
DescriptionCPM4 PCIe1 Attributes (program with design tools)

CPM4_PCIE1_ATTR Module Register Summary

Register NameOffset AddressWidthTypeReset ValueDescription
MISC_CTRL0x0000000000 1rwNormal read/write0x00000000MISC_CTRL
ISR0x000000001032wtcReadable, write a 1 to clear0x00000000Interrupt Status Register. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
IMR0x000000001432roRead-only0x00000003Interrupt Mask Register. This is a read-only location and can be atomically altered by either the IDR or the IER.
IER0x000000001832woWrite-only0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
IDR0x000000001C32woWrite-only0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
CRM_CORE_CLK_FREQ0x000000003032rwNormal read/write0x00000000Core Clock Frequency:
00001b = 250 MHz
00010b = 500 MHz
00100b = 1000 MHz (temp:for Gen4x16 PCIEA only)
All other encodings are Reserved
CRM_USER_CLK_FREQ0x000000003432rwNormal read/write0x00000000User clock/User Clk2 frequency: Valid settings are:
000b = 62.5/62.5 MHz,
001b = 125/125 MHz,
010b = 250/250 MHz,
011b = Reserved if CRM_CORE_CLK_FREQ==00001 b
011b = 250/500 MHz if CRM_CORE_CLK_FREQ ==00010b and AXISTEN_IF_WIDTH == 11b
011b = 500/1000 MHz if CRM_CORE_CLK_FREQ ==00100b and AXISTEN_IF_WIDTH == 11b (temp:for Gen4x16 PCIEA only)
100b = 500/500 if
if CRM_CORE_CLK_FREQ ==00010b and AXISTEN_IF_WIDTH == 10b
All other encodings are reserved.
AXISTEN_IF_WIDTH0x000000003832rwNormal read/write0x00000000AXI Streaming Enhanced Inteface Width: Valid settings are: 00b = 64b, 01b = 128b, 10b = 256b, 11b = 512b
AXISTEN_IF_EXT_5120x000000003C32rwNormal read/write0x00000000AXI Stream Enhanced Interface Enable External 512b
Interface: When TRUE, CRM_CORE_CLK_FREQ_500 is TRUE and AXISTEN_IF_WIDTH is 10b (256b), enables external
512b AXI4ST soft shim.
AXISTEN_IF_EXT_512_CQ_STRADDLE0x000000004032rwNormal read/write0x00000000AXI Stream Enhanced Interface Enable External 512b
Interface CQ Straddle Enable: When TRUE, and AXISTEN_IF_EXT_512 is TRUE, then Straddle is enabled on CQ interface.
AXISTEN_IF_EXT_512_CC_STRADDLE0x000000004432rwNormal read/write0x00000000AXI Stream Enhanced Interface Enable External 512b
Interface CC Straddle Enable: When TRUE, and AXISTEN_IF_EXT_512 is TRUE, then Straddle is enabled on CC interface.
AXISTEN_IF_EXT_512_RQ_STRADDLE0x000000004832rwNormal read/write0x00000000AXI Stream Enhanced Interface Enable External 512b
Interface RQ Straddle Enable: When TRUE, and AXISTEN_IF_EXT_512 is TRUE, then Straddle is enabled on RQ
interface.
AXISTEN_IF_EXT_512_RC_STRADDLE0x000000004C32rwNormal read/write0x00000000AXI Stream Enhanced Interface Enable External 512b
Interface RC Straddle Enable: When TRUE, and AXISTEN_IF_EXT_512 is TRUE, then Straddle is enabled on RC
interface.
AXISTEN_IF_CQ_ALIGNMENT_MODE0x000000005032rwNormal read/write0x00000000AXI Streaming Enhanced Inteface CQ Alignment: Determines the data alignment mode for the CQ interface: 00b = Dword-aligned mode, 01b = 256b-address-aligned mode,
10b = 128b-address-aligned mode, 11b = Reserved. Encoding 10b is suppored only when
AXISTEN_IF_EXT_512=TRUE. Encoding 01b is not suppored only when
AXISTEN_IF_EXT_512=TRUE.
AXISTEN_IF_CC_ALIGNMENT_MODE0x000000005432rwNormal read/write0x00000000AXI Streaming Enhanced Inteface CC Alignment: Determines the data alignment mode for the CC interface: 00b = Dword-aligned mode, 01b = 256b-address-aligned mode,
10b = 128b-address-aligned mode, 11b = Reserved. Encoding 10b is suppored only when
AXISTEN_IF_EXT_512=TRUE. Encoding 01b is not suppored only when
AXISTEN_IF_EXT_512=TRUE.
AXISTEN_IF_RQ_ALIGNMENT_MODE0x000000005832rwNormal read/write0x00000000AXI Streaming Enhanced Inteface RQ Alignment:
Determines the data alignment mode for the RQ interface: 00b = Dword-aligned mode, 01b = 256b-address-aligned mode,
10b = 128b-address-aligned mode, 11b = Reserved. Encoding 10b is suppored only when
AXISTEN_IF_EXT_512=TRUE. Encoding 01b is not suppored only when
AXISTEN_IF_EXT_512=TRUE.
AXISTEN_IF_RC_ALIGNMENT_MODE0x000000005C32rwNormal read/write0x00000000AXI Streaming Enhanced Inteface RC Alignment:
Determines the data alignment mode for the RC interface: 00b = Dword-aligned mode, 01b = 256b-address-aligned mode,
10b = 128b-address-aligned mode, 11b = Reserved. Encoding 10b is suppored only when
AXISTEN_IF_EXT_512=TRUE. Encoding 01b is not suppored only when
AXISTEN_IF_EXT_512=TRUE. Encodings 01b and 10b can used only if AXISTEN_IF_RQ_ALIGNMENT_MODE is set to 01b or 10b.
AXISTEN_IF_RC_STRADDLE0x000000006032rwNormal read/write0x00000000Received
AXISTEN frame straddle:
When TRUE, enables
received
requester completion AXISTEN frames to straddle single cycle transfer when AXISTEN_IF_WIDTH is configured to 256b. When FALSE, straddle feature disabled.
AXISTEN_IF_ENABLE_RX_MSG_INTFC0x000000006432rwNormal read/write0x00000000Received AXISTEN message interface enable: When set to 0, received messages are delivered through the CQ interface.
When set to 1, these are delivered through the receive message interface.
AXISTEN_IF_ENABLE_MSG_ROUTE0x000000006832rwNormal read/write0x00000000Received AXISTEN message routing
Enable the routing of message TLPs to the user through the AXI CQ interface.
A bit value of 1 enables routing of the message TLP to the user.
Messages are always decoded by the message decoder.
Bit 0 - ERR_COR,
Bit 1 - ERR_NONFATAL,
Bit 2 - ERR_FATAL,
Bit 3 - Assert_INTA and Deassert_ INTA,
Bit 4 - Assert_INTB and Deassert_ INTB,
Bit 5 - Assert_INTC and Deassert_ INTC,
Bit 6 - Assert_INTD and Deassert_ INTD,
Bit 7 - PM_PME,
Bit 8 - PME_TO_Ack,
Bit 9 - PME_Turn_Off,
Bit 10 - PM_Active_State_Nak,
Bit 11 - Set_Slot_Power_Limit,
Bit 12 - Latency Tolerance Reporting (LTR),
Bit 13 - Reserved,
Bit 14 - Unlock,
Bit 15 - Vendor_Defined Type 0,
Bit 16 - Vendor_Defined Type 1,
Bit 17 - Invalid Request, Invalid Completion, Page, Request, PRG Response,
AXISTEN_IF_RX_PARITY_EN0x000000006C32rwNormal read/write0x00000000AXI Rx Interface Parity Enable. Used in conjunction with LL_RX_TLP_PARITY_GEN
TRUE --
parity
is enabled
FALSE -- parity is disabled.
AXISTEN_IF_TX_PARITY_EN0x000000007032rwNormal read/write0x00000000AXI Tx Interface Parity Enable. Used in conjunction with LL_TX_TLP_PARITY_CHK
TRUE --
parity
is enabled
FALSE -- parity is disabled.
AXISTEN_IF_ENABLE_CLIENT_TAG0x000000007432rwNormal read/write0x00000000AXI Streaming Enhanced Inteface Tag management option for RQ interface: When this attribute is FALSE, Tag management for Non-Posted transactions initiated from the requester request interface is performed by the PCIe Hard Block. That is, for each Non-Posted request, the core allocates the Tag for the transaction and communicates it to the client.When this attribute set to TRUE,
internal tag management is disabled, allowing the user to supply the tag to be used for each request. The user must present the Tag field in the Request descriptor header in the range 0-31 when attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED is FALSE, while Tag field must be in the range 0-255 when attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED is TRUE. When this attribute is TURE and attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED is TRUE, attribute AXISTEN_IF_ENABLE_256_TAGS should be set to TRUE.
AXISTEN_IF_ENABLE_256_TAGS0x000000007832rwNormal read/write0x00000000AXI Streaming Enhanced Inteface Tag management option to enable 256 Tags for RQ interface. When this attribute is TRUE, Tag Management unit will allocate from a pool of 256 Tags. When this attribute is FALSE, Tag Management unit will allocate from a pool of 128 Tags.
AXISTEN_IF_ENABLE_RX_TAG_SCALING0x000000007C32rwNormal read/write0x00000000AXI Streaming Enhanced Inteface Rx Tag Scaling:
AXISTEN_IF_ENABLE_TX_TAG_SCALING0x000000008032rwNormal read/write0x00000000AXI Streaming Enhanced Inteface Tx Tag Scaling:
AXISTEN_IF_COMPL_TIMEOUT_REG00x000000008432rwNormal read/write0x00000000Completion Timeout Limit Register #0: This register contains the timeout value used to detect a completion timeout event for a request originated by the core from its AXI master interface, when sub-range 1 is programmed in the Device Control 2 Register.
AXISTEN_IF_COMPL_TIMEOUT_REG10x000000008832rwNormal read/write0x00000000Completion Timeout Limit Register #1: This register contains the timeout value used to detect a completion timeout event for a request originated by the core from its AXI master interface, when sub-range 2 is programmed in the Device Control 2 Register.
AXISTEN_IF_LEGACY_MODE_ENABLE0x000000008C32rwNormal read/write0x00000000Enable Legacy Endpoint Mode: When TRUE, if PL_UPSTREAM_FACING is TRUE, then core is configured as a Legacy Endpoint and will
forward Locked Transactions through the AXI target interface, and generate Locked Completions in response to them. If PL_UPSTREAM_FACING is FALSE, then user can generate Locked Read Transactions as a Master. When FALSE, core is configured as a PCIe Endpoint.
AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK0x000000009032rwNormal read/write0x00000000Enable Requestor ID Checking of Received TLPs: When set to TRUE, the core will check the RID of the incoming Message TLPs that are routed by ID, against the RIDs of its enabled Functions. Any messages with an RID mismatch are handled as Unsupported Requests and discarded within the core. When this bit is FALSE, the core will not check the RIDs of received Message TLPs and will forward them to the AXISTEN interface. This attribute is applicable only when the core is configured as an Endpoint.
AXISTEN_IF_MSIX_TO_RAM_PIPELINE0x000000009432rwNormal read/write0x00000000To MSIX RAM Pipeline: When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE is TRUE, a TRUE indicates presence of a external CLB flip-flop pipeline stage on interface signals from Hard Block to BlockRAMs. FALSE indicates that there is no pipeline is present.
AXISTEN_IF_MSIX_FROM_RAM_PIPELINE0x000000009832rwNormal read/write0x00000000From MSIX RAM
Pipeline: When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE is TRUE, a TRUE indicates presence of a external CLB flip-flop pipeline stage on interface signals to Hard Block from BlockRAMs. FALSE indicates that there is no pipeline is present.
AXISTEN_IF_MSIX_RX_PARITY_EN0x000000009C32rwNormal read/write0x00000000AXI Rx Interface MSIX Parity Enable. Used in conjunction with LL_RX_TLP_PARITY_GEN and AXISTEN_IF_RX_PARITY_EN
TRUE --
parity
is enabled
FALSE -- parity is disabled.
AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE0x00000000A032rwNormal read/write0x00000000MSIX Internal Tables Enable: When this attribute is set to TRUE, the MSIX Table and Pending Bit Array (PBA) functions are implemented within the Block (in MSIX RAM).
When it is set to FALSE, the MSIX Table and PBA are implemented in user logic.
AXISTEN_IF_INTERNAL_MSIX_VECTORS_PER_FUNCTION0x00000000A432rwNormal read/write0x00000000MSIX Internal Tables Vectors Per Function:
0h - 8 vectors per function
1h - 16 vectors per function
2h - 32 vectors per function
3h - 64 vectors per function
AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT0x00000000A832rwNormal read/write0x00000000AXI Stream Enhanced Interface Simulation Short Completion Timeout: When TRUE, Non Posted Completion Timeouts are scaled down by a factor of ~1000.
AXISTEN_IF_CCIX_TX_REGISTERED_TREADY0x00000000AC32rwNormal read/write0x00000000AXI Stream CCIX Tx Registered tready: This attribute defines the flow control behavior on the CCIX Transaction Layer Transmit Interface.
When this attribute is set to 0b, the interface supports that standard AXI Stream tvalid-tready protocol.
When set to 1b, it supports a modified protocol where the response to ready is delayed by 2 cycles.
AXISTEN_IF_CCIX_TX_CREDIT_LIMIT0x00000000B032rwNormal read/write0x00000000AXI CCIX TX Credits: This attribute defines the maximum number of flow control credits issued by the TL on the CCIX Transaction Layer Transmit Interface.
Its value is defined in terms of number of AXI4 beats (full or partial).
The setting of this attribute is implementation-dependent, with a minimum value of 8 and a maximum value of 63.
AXISTEN_IF_CCIX_RX_CREDIT_LIMIT0x00000000B432rwNormal read/write0x00000000AXI CCIX RX Credits: This attribute defines the maximum number of flow control credits issued by the CCIX transmit-side application.
Its value controls the width of the credit counters in the TL block. Its minimum value is 2 and the maximum is 255 (Soft logic use only).
AXISTEN_IF_CQ_POISON_DISCARD_DISABLE0x00000000B832rwNormal read/write0x00000000AXISTEN_IF_CQ_POISON_DISCARD_DISABLE. When it is set to TRUE, poisoned TLPs are not discarded by AXIST CQ Interface, but passed to the Users with Descriptor Bit[79] set. When it is set to FALSE, no poisoned TLP is sent to the Users on AXIST CQ Interface.
AXISTEN_IF_EXTEND_CPL_TIMEOUT0x00000000BC32rwNormal read/write0x00000000Extend Completion Timeouts: When [1:0] is set to 01, Completion Timeout range is extended and becomes 64ms to 4s. When [1:0] is set to 10, Completion Timeout range is extended and becomes 128ms to 8s. Otherwise, the default timeout range is 16ms to 1s.
AXISTEN_IF_RQ_CC_REGISTERED_TREADY0x00000000C032rwNormal read/write0x00000000Allows
interface logic to use registered
(CLB Flop) version of tready (for timing closure reasons) on RQ and CC interfaces (not AXIST spec compliant). 0=Disables registed tready mode of opration. tready on RQ and CC interfaces must be directly used to control data source (AXIST spec compliant).
AXISTEN_IF_ENABLE_10B_TAGS0x00000000C432rwNormal read/write0x00000000Enable Tag Scaling: When TRUE, enables 10b Tags width. When FALSE, Tag width is 8b/5b.
AXISTEN_IF_PASID_UR_CHECK_DISABLE0x00000000C832rwNormal read/write0x00000000Disable PASID UR Check: When TRUE, disables UR check on PASID for CQ.
AXISTEN_IF_CQ_EN_POISONED_MEM_WR0x00000000CC32rwNormal read/write0x00000000AXI Stream Enable Presentation of Poisoned Memory Write on CQ interface: When this attribute is set to TRUE, all reeived Poisoned Memory Write TLPs targeted at any of the Functions will be presented on the CQ Interface (with the Poison bit set in the descriptor to indicate its status). When the attribute is set to FALSE,
all received poisoned Memory Write transactions will be discarded (not presetned on the CQ interface). This setting has no effect on the reporting of Poisoned TLP errors, and setting it to TRUE, simply provides the received poisoned packet and payload to the user for debug/diagnostics purposes.
AXISTEN_USER_SPARE0x00000000D032rwNormal read/write0x00000000AXI Stream Spare Bits.
Bit0: 1b: Disable Completion Table Poisoned Bit check (Error Code 1); 0b: Enable
Bit1: 1b: Disable Completion Table Completion Status check (Error Code 2); 0b: Enable
Bit2: 1b: Disable Completion Table Byte Count check (Error Code 3); 0b: Enable
Bit3: 1b: Disable Completion Table
RID/RC/Attr check (Error Code 4); 0b: Enable
Bit4: 1b: Disable Completion Table
Low Address check (Error Code 5); 0b: Enable
Bit5: 1b: Disable Completion Table
Invalid Tag check (Error Code 6); 0b: Enable
Bit6: 1b: Disable Completion Table
Function-Level Reset check (Error Code 8); 0b: Enable
Bit7: 1b: Disable Completion Table Full check for Client Tag mode; 0b: Enable
Bit8: (PCIEA only) 1b: Enable AXIST
RQ/CC pipeline FIFO; 0b: Disable
Bit9: (PCIEA only) 1b: Enable AXIST RQ/CC pipeline Registered Tready. 0b: Disabled (For PCIEA only AXISTEN_IF_RQ_CC_REGISTERED_TREADY is deprecated)
Bit10: (Switch only) 1b: Disable Low Address Fix for Translation Request. 0b: Enable
PM_ASPML0S_TIMEOUT0x00000000D432rwNormal read/write0x00000000L0S Timeout Limit Register: Timeout value for transitioning to the L0S power state. If the transmit side has been idle for this interval, the core will transmit the idle sequence on the link and transition the state of the link to L0S. Contains the timeout value (in units of4 ns) for transitioning to the L0S power state Setting it to 0 permanently disables the transition to the L0S power state.
PM_L1_REENTRY_DELAY0x00000000D832rwNormal read/write0x00000000L1 State Re-entry Delay Register: Time (in units of 4 ns) the core will wait before it re-enters the L1 state if its link partner transitions the link to L0 while all the Functions of the core are in D3 power state. The core will change the power state of the link from L0 to L1 if no activity is detected both on the transmit and receive sides before this interval, while all Function are in D3 state and the link is in L0. Setting this register to 0 disables re-rentry to L1 state if the link partner returns the link to L0 from L1 when all the Functions of the core are in D3 state. This register control only the re-entry to L1. This register control only the re-entry to L1. The initial transition to L1 always occurs when the all the Functions of the core are set to the D3 state. The defaults are nominal values that should not be changed.
PM_ASPML1_ENTRY_DELAY0x00000000DC32rwNormal read/write0x00000000ASPM L1 Entry Timeout Delay Register: Contains the timeout value (in units of 4 ns) for transitioning to the L1 power state. Setting it to 0 permanently disables the transition to the L1 power state. The defaults are nominal values that should not be changed.
PM_ENABLE_SLOT_POWER_CAPTURE0x00000000E032rwNormal read/write0x00000000When set to TRUE, and configured as Endpoint, the core will capture the Slot Power Limit Value and Slot Power Limit Scale parameters from a Set_Slot_Power_Limit message received in the Device Capabilities Register. When this bit is 0, the capture is disabled.
PM_PME_TURNOFF_ACK_DELAY0x00000000E432rwNormal read/write0x00000000Time in microseconds between the core receiving a PME_Turn_Off message TLP and sending a PME_ TO_Ack response to it. This field must be set to a non-zero value to enable the core to send the response. Setting this field to 0 suppresses the cores response to the PME_Turn_Off message, so that the user may transmit the PME_TO_Ack message through the AXI interface.
PL_UPSTREAM_FACING0x00000000E832rwNormal read/write0x00000000Physical Layer Mode: TRUE specifies upstream-facing port.
FALSE specifies downstream-facing port. This setting is propagated to all layers in the core.
PL_LINK_CAP_MAX_LINK_WIDTH0x00000000EC32rwNormal read/write0x00000000Maximum Link Width.
Valid settings are:
000001b x1, 00010b x2, 00100b x4, 01000b x8, 10000b x16. All other encodings are reserved. This setting is propagaed to all layers in the design.
PL_LINK_CAP_MAX_LINK_SPEED0x00000000F032rwNormal read/write0x00000000Maximum Link Speed. Valid settings are:
0001b = Gen1, 0010b = Gen2, 0100b = Gen3, 1000b = Gen4. All other encodings are reserved. This setting is propagated to all layers in the design.
PL_DISABLE_DC_BALANCE0x00000000F432rwNormal read/write0x00000000Disable Gen3 or Gen4 DC Balance: Disabled transmission of special symbols when set to TRUE. Used for debug.
PL_DISABLE_EI_INFER_IN_L00x00000000F832rwNormal read/write0x00000000When set to TRUE disables the inferring of electrical idle in the L0 state. Electrical idle is inferred when no flow control updates and no SKP sequences are received within an interval of 128 us. This bit should not be set to TRUE during normal operation, but may be used for in system debug.
PL_N_FTS0x00000000FC32rwNormal read/write0x00000000Sets the number of FTS OS, advertised in the TS1 Ordered Sets. Value supported by Xilinx GTs is 255.
PL_DISABLE_UPCONFIG_CAPABLE0x000000010032rwNormal read/write0x00000000This attribute disables the upconfigure capability when set to TRUE and enables the upconfigure capability when set to FALSE.
In EP Mode this must be set to False (1b0). In RP Mode this must be set to TRUE (1b1).
PL_DISABLE_RETRAIN_ON_FRAMING_ERROR0x000000010432rwNormal read/write0x00000000This attribute disables link retrain on any and all framing error at Gen3 or Gen4 speeds due to Rx framing error detected, behavior when set to TRUE and enables it when set to FALSE. Used for debug.
PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR0x000000010832rwNormal read/write0x00000000Disables link retrain for specific framing error reasons when set to 1b
bit0: Rx Link Bad Frame Start Error (BFS Error (Optional by Spec))
bit1: Rx FCRC & Parity Error (FCRCP Error(Optional by Spec))
bit2: Rx TLP Length Error (TLPL Error (Optional by Spec))
bit3: Rx Multiple STP Error (MSTP Error (Optional by Spec))
bit4: Rx Out of Place EDB (OOPEDB Error (Optional by Spec))
bit5: Rx Ordered Set After EDS Error (OSAEDS Error (Optional by Spec))
bit6: Rx Multiple SDP Error (MSDP Error (Optional by Spec))
bit7: Rx OS after SDS Error (RXOSASDS Error(Required by Spec))
bit8: Rx Unknown Block Type Error (RXUNBT Error(Required by Spec))
bit9: Rx OS without EDS Error (RXOSWOEDS Errror(Reqquired by Spec))
bit10: Rx Data Block After EDS Error (DBAEDS Error(Required by Spec))
bits11-15: Reserved
PL_DISABLE_RETRAIN_ON_EB_ERROR0x000000010C32rwNormal read/write0x00000000This attribute disables link retrain on error detection in the (elastic buffer in) the deskew buffer behavior when set to TRUE and enables it when set to FALSE. Used for debug.
PL_REPORT_ALL_PHY_ERRORS0x000000011032rwNormal read/write0x00000000Disables reporting for specific phy error reporting when set to 1b
bit0 - Gen1/2 Disparity (pipe_rx{n}_status == 111b)
bit1 - Elastic Buf Undeflow (pipe_rx{n}_status == 110b)
bit2 - Overflow (pipe_rx{n}_status == 101b)
bit3
- Gen3 Disparity (pipe_rx{n}_status == 100b)
bits 4-7 - Reserved
PL_LANE0_EQ_CONTROL0x000000011832rwNormal read/write0x00000000Lane#0 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint. Lower 16b for Gen3 operation and Upper 16b for Gen4 operation.Bits 7, 15, 23, 31 are unused.
PL_LANE1_EQ_CONTROL0x000000011C32rwNormal read/write0x00000000Lane#1 Equalization Control Register:
Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE2_EQ_CONTROL0x000000012032rwNormal read/write0x00000000Lane#2 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE3_EQ_CONTROL0x000000012432rwNormal read/write0x00000000Lane#3 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE4_EQ_CONTROL0x000000012832rwNormal read/write0x00000000Lane#4 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint. Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE5_EQ_CONTROL0x000000012C32rwNormal read/write0x00000000Lane#5 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation.Bits 7, 15, 23, 31 are unused.
PL_LANE6_EQ_CONTROL0x000000013032rwNormal read/write0x00000000Lane#6 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE7_EQ_CONTROL0x000000013432rwNormal read/write0x00000000Lane#7 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE8_EQ_CONTROL0x000000013832rwNormal read/write0x00000000Lane#8 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE9_EQ_CONTROL0x000000013C32rwNormal read/write0x00000000Lane#9 Equalization Control Register:
Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE10_EQ_CONTROL0x000000014032rwNormal read/write0x00000000Lane#10 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE11_EQ_CONTROL0x000000014432rwNormal read/write0x00000000Lane11 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE12_EQ_CONTROL0x000000014832rwNormal read/write0x00000000Lane#12 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE13_EQ_CONTROL0x000000014C32rwNormal read/write0x00000000Lane#13 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE14_EQ_CONTROL0x000000015032rwNormal read/write0x00000000Lane#14 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint.
Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_LANE15_EQ_CONTROL0x000000015432rwNormal read/write0x00000000Lane#15 Equalization Control Register: Sets the appropriate lane specific entry in the
Equalization Control Register in Secondary PCI Express Extended Capability Header. Bit[3:0] - Downstream Port Transmitter Preset, Bit[6:4] Downstream Port Receiver Preset Hint, Bit[11:8] Upstream Port Transmitter Preset, Bit[14:12] Upstream Port Receiver Preset Hint. Lower 16b for Gen3 operation and Upper 16b for Gen4 operation. Bits 7, 15, 23, 31 are unused.
PL_EQ_BYPASS_PHASE230x000000015832rwNormal read/write0x00000000Bypass Equalization Phases 2 & 3: When TRUE, and
if PL_UPSTREAM_FACING is FALSE, then Bypass optional EQ Phases. Bit0 if for Gen3 operation, Bit1 is for Gen4 operation.
PL_EQ_ADAPT_ITER_COUNT0x000000015C32rwNormal read/write0x00000000Link Partner Transmitter Adaptive Equilization Iteration Count: When in EQ Phase-2 for EP and Phase-3 for RP, this is the maximum number of iterations of Adaptive Equilization attempted before exiting the Recovery.EQ phase. Supported range 2-31
PL_EQ_SHORT_ADAPT_PHASE0x000000016432rwNormal read/write0x00000000Shorten the Receive Adaptation Phase: When set to TRUE, EQ Phase-2 for EP and Phase-3 for RP will return the received Tx Preset OR Coefficients as the the new proposed settings. Anticipate use for simulation speed-up and debug purposes.
PL_EQ_ADAPT_DISABLE_COEFF_CHECK0x000000016832rwNormal read/write0x00000000Disable checks on Received Coefficients: When set to TRUE, received coefficient cheking is disabled (no rejection) during EQ Phase-3 for EP and EQ Phase-2 for RP. Bit0 if for Gen3 operation, Bit1 is for Gen4 operation.
PL_EQ_ADAPT_DISABLE_PRESET_CHECK0x000000016C32rwNormal read/write0x00000000Disable checks on Received Presets: When set to TRUE, received preset cheking is disabled (no rejection) during EQ Phase-3 for EP and EQ Phase-2 for RP. Bit0 if for Gen3 operation, Bit1 is for Gen4 operation.
PL_EQ_DEFAULT_TX_PRESET0x000000017032rwNormal read/write0x00000000Default Gen3/Gen4 Tx Preset: This value is used in transmitted TS1s by Endpoint in EQ Phase0,if no EQ TS2 are receied during EQ Phase0. bits[3:0] are for Gen3 operation, bits[7:4] are for Gen4 operation. Others bits are reserved.
PL_EQ_DEFAULT_RX_PRESET_HINT0x000000017432rwNormal read/write0x00000000Default Gen3/Gen4 Rx Preset Hint: This value is used in transmitted TS1s by Endpoint in EQ Phase0,if no EQ TS2 are receied during EQ Phase0. bits[2:0] are for Gen3 operation, bits[5:3] are for Gen4 operation. Xilinx GTs do not require a Rx Preset Hint, therefore, UNUSED.
PL_EQ_DISABLE_MISMATCH_CHECK0x000000017832rwNormal read/write0x00000000Disable Mismatch Check in Recovery RecvrLock in Upstream Port: Disables Spec required check of Rx Preset in Upstream Port Recovery ReceiverLock state.
PL_EQ_RX_ADV_EQ_PER_DATA_RATE_ENABLE0x000000017C32rwNormal read/write0x00000000Rx Adaptation EQ Mode per Speed Enable: Bit = 0b, Adv EQ disabled. Bit = 1b, Adv EQ enabled, only when PL_EQ_RX_ADAPTATION_MODE = 101b or 110b.
bit[0] = 8 GT/s
bit[1] = 16 GT/s
bit[2] = 20 GT/s
bit[3] = 25 GT/s
PL_EQ_RX_ADAPTATION_MODE0x000000018032rwNormal read/write0x00000000Rx Adaptation EQ Mode:
bit[0] - 1b = Enable Original constant single Preset (PL_EQ_DEFAULT_TX_PRESET)
bit[1] - 1b = Enable Two Presets, second Preset (PL_EQ_DEFAULT_TX_PRESET2) used on rejection of the first Preset (PL_EQ_DEFAULT_TX_PRESET).
bit[2] - 1b = Enable Advanced EQ.
Supported Options:
3b001 => Normal EQ for all modes and data rates
3b010 => Backup EQ for all modes and data rates
3b101 => Adv + Normal EQ, subject to data rates selected in PL_EQ_RX_ADV_EQ_PER_DATA_RATE_ENABLE (used with EDR mode)
3b110 => Adv + Backup EQ, subject to data rates selected in PL_EQ_RX_ADV_EQ_PER_DATA_RATE_ENABLE (used with EDR mode)
All others are reserved
PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN40x000000019432rwNormal read/write0x00000000Downstream Port Auto Speed Change to Gen4: When FALSE enable Downstream Port to autonomously change speed to Gen4. When TRUE will require software to issue "link retrain". Usually set to TRUE only to overcome VIP modelling limitations.
PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN30x000000019832rwNormal read/write0x00000000Downstream Port Auto Speed Change to Gen3: When FALSE enable Downstream Port to autonomously change speed to Gen3. When TRUE will require software to issue "link retrain". Usually set to TRUE only to overcome VIP modelling limitations.
PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN20x000000019C32rwNormal read/write0x00000000Downstream Port Auto Speed Change to Gen2: When FALSE enable Downstream Port to autonomously change speed to Gen2. When TRUE will require software to issue "link retrain". Usually set to TRUE only to overcome VIP modelling limitations.
PL_DESKEW_ON_SKIP_IN_GEN120x00000001A032rwNormal read/write0x00000000Deskew using SKP OS in Gen1 and Gen2 speed: When TRUE enable deskew using SKP OS. When FALSE disable this feature. Re-Used this Rx L0s Deskew ECO (SI# 948565)
PL_INFER_EI_DISABLE_REC_RC0x00000001A432rwNormal read/write0x00000000Infer EI Disable in REC RC. Used for debug.
PL_INFER_EI_DISABLE_REC_SPD0x00000001A832rwNormal read/write0x00000000Infer EI Disable in REC SPEED. Used for debug.
PL_INFER_EI_DISABLE_LPBK_ACTIVE0x00000001AC32rwNormal read/write0x00000000Infer EI Disable in Loopback Active. Used for debug.
PL_RX_ADAPT_TIMER_RRL_GEN30x00000001B032rwNormal read/write0x00000000Xilinx GT implementation Specific Rx Adaptation Timeout state before Recovery.RcvrLock when current speed is Gen3 (in milli seconds). Value of 0h disables the timer. Allowed values are 0h to Fh. Must
be set to 0 when PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS is FALSE
PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS0x00000001B432rwNormal read/write0x00000000When in Xilinx GT implementation Specific Rx Adaptation Timeout state before Recovery.RcvrLock at Gen3 speed, Clobber Tx Training Sets. Bit0 if for Gen3 operation, Bit1 is for Gen4 operation.
PL_RX_ADAPT_TIMER_RRL_GEN40x00000001B832rwNormal read/write0x00000000Xilinx GT implementation Specific Rx Adaptation Timeout before Recovery.RcvrLock when current speed is Gen4 (in milli seconds). Value of 0h disables the timer. Allowed values are 0h to Fh.
Must
be set to 0 when PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS is FALSE
PL_RX_ADAPT_TIMER_CLWS_GEN30x00000001BC32rwNormal read/write0x00000000Xilinx GT implementation Specific Rx Adaptation Timeout state before Configuration.LinkWidthStart when current speed is Gen3 (in milli seconds). Value of 0h disables the timer. Allowed values are 0h to Fh
PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS0x00000001C032rwNormal read/write0x00000000When in Xilinx GT implementation Specific Rx Adaptation Timeout state before
Configuration.LinkWidthStart at Gen3 speed, Clobber Tx Training Sets. Bit0 if for Gen3 operation, Bit1 is for Gen4 operation.
PL_RX_ADAPT_TIMER_CLWS_GEN40x00000001C432rwNormal read/write0x00000000Xilinx GT implementation Specific Rx Adaptation Timeout state before Configuration.LinkWidthStart when current speed is Gen4 (in milli seconds). Value of 0h disables the timer. Allowed values are 0h to Fh
PL_DISABLE_LANE_REVERSAL0x00000001C832rwNormal read/write0x00000000Disables Lane Reversal Feature
PL_CFG_STATE_ROBUSTNESS_ENABLE0x00000001CC32rwNormal read/write0x00000000Enables Increased Rx TS Count 2 to 4 in Cfg LTSSM States. TRUE by default. FALSE for Compliance testing. Used for debug.
PL_DEEMPH_SOURCE_SELECT0x00000001D432rwNormal read/write0x00000000Applicable to Upstream & Downsteam Ports.
When FALSE:
Selects value of Selectable De-emphasis (bit4, symbol4) recived on TS2s in Recovery.RecvrCfg.
When TRUE: if PL_UPSTREAM_FACING is TRUE, selects value presented on pl_gen2_upstream_prefer_deemph, else, if PL_UPSTREAM_FACING is FALSE, then selects value of Selectable De-emphasis (bit6) of Link Control 2 Register.
When PL_UPSTREAM_FACING is TRUE, default should be FALSE.
When PL_UPSTREAM_FACING is FALSE default should be TRUE
PL_EXIT_LOOPBACK_ON_EI_ENTRY0x00000001D832rwNormal read/write0x00000000Exit Lookback if Entry to EI Detected on Rx When FALSE used to optionally disable exit from Loopback Active when Electrical Idle is detected on Rx.
PL_QUIESCE_GUARANTEE_DISABLE0x00000001DC32rwNormal read/write0x00000000Disable Quiesce Guarantee
When TRUE disables assertion of Quiesce Guarantee (bit 6) on transmitted TS2s in Recovery.RcvrCfg (together with Request Equalization (bit 7) and Equalization Request Data Rate (bit 5) (in Gen4 speed)) when current speed is Gen3 or Gen4. When FALSE Quiesce Guarantee (bit 6) is set, together with Request Equalization (bit 7) and Equalization Request Data Rate (bit 5) (in Gen4 speed.
PL_SRIS_ENABLE0x00000001E032rwNormal read/write0x00000000Enable Separate Reference Clock Indepenent SSC (SRIS) Mode When TRUE enabled SRIS functionality in the Physical Layer. Normal operation when FALSE.
PL_SRIS_SKPOS_GEN_SPD_VEC0x00000001E432rwNormal read/write0x00000000Link Capabilities 2 Register: : Lower SKP OS Generation Supported Speeds Vector Used by PL when SRIS is enabled.
PL_SRIS_SKPOS_REC_SPD_VEC0x00000001E832rwNormal read/write0x00000000Link Capabilities 2 Register: : Lower SKP OS Reception Supported Speeds Vector Used by PL when SRIS is enabled.
PL_RETIMER_PRESENCE_DETECTION_SUPPORTED0x00000001EC32rwNormal read/write0x00000000Link Capabilities 2 Register: : Retimer Presence Detect Supported. Enabled when TRUE.
PL_TWO_RETIMER_PRESENCE_DETECTION_SUPPORTED0x00000001F032rwNormal read/write0x00000000Link Capabilities 2 Register: : Two Retimer Presence Detect Supported. Enabled when TRUE.
PL_CTRL_SKP_GEN_ENABLE0x00000001F432rwNormal read/write0x00000000Control SKP OS Genertation Enable:
PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE0x00000001F832rwNormal read/write0x00000000Control SKP OS Parity and CRC Check Disable:
PL_SIM_FAST_LINK_TRAINING0x00000001FC32rwNormal read/write0x00000000Fast Link Training for Simulations: Link training time is
shortened to facilitate fast simulation of the design. Enabling this bit has the following effects:
1. When PL_SIM_FAST_LINK_TRAINING[0] = 1b, all 1 ms, 2 ms, 12 ms, 24 ms, 32 ms and 48 ms timeout intervals in the LTSSM are shortened by a factor of 512.
2. When PL_SIM_FAST_LINK_TRAINING[1] = 1b, in the Polling.Active, Recovery.RecLock (Ext Sync Enabled) state of the LTSSM, only 16 training sequences are required to be transmitted (Instead of 1024) to make the transition to the Configuration state.
Must be set to 00b for non-simulation use.
PL_EQ_TX_PRECUR_00x000000020032rwNormal read/write0x00000000Tx Pre-Cursor for Preset0
PL_EQ_TX_PRECUR_10x000000020432rwNormal read/write0x00000000Tx Pre-Cursor for Preset1
PL_EQ_TX_PRECUR_20x000000020832rwNormal read/write0x00000000Tx Pre-Cursor for Preset2
PL_EQ_TX_PRECUR_30x000000020C32rwNormal read/write0x00000000Tx Pre-Cursor for Preset3
PL_EQ_TX_PRECUR_40x000000021032rwNormal read/write0x00000000Tx Pre-Cursor for Preset4
PL_EQ_TX_PRECUR_50x000000021432rwNormal read/write0x00000000Tx Pre-Cursor for Preset5
PL_EQ_TX_PRECUR_60x000000021832rwNormal read/write0x00000000Tx Pre-Cursor for Preset6
PL_EQ_TX_PRECUR_70x000000021C32rwNormal read/write0x00000000Tx Pre-Cursor for Preset7
PL_EQ_TX_PRECUR_80x000000022032rwNormal read/write0x00000000Tx Pre-Cursor for Preset8
PL_EQ_TX_PRECUR_90x000000022432rwNormal read/write0x00000000Tx Pre-Cursor for Preset9
PL_EQ_TX_PRECUR_A0x000000022832rwNormal read/write0x00000000Tx Pre-Cursor for PresetA
PL_EQ_TX_PRECUR_B0x000000022C32rwNormal read/write0x00000000Tx Pre-Cursor for PresetB
PL_EQ_TX_PRECUR_C0x000000023032rwNormal read/write0x00000000Tx Pre-Cursor for PresetC
PL_EQ_TX_PRECUR_D0x000000023432rwNormal read/write0x00000000Tx Pre-Cursor for PresetD
PL_EQ_TX_PRECUR_E0x000000023832rwNormal read/write0x00000000Tx Pre-Cursor for PresetE
PL_EQ_TX_PRECUR_F0x000000023C32rwNormal read/write0x00000000Tx Pre-Cursor for PresetF
PL_EQ_TX_POSTCUR_00x000000024032rwNormal read/write0x00000000Tx POST-Cursor for Preset0
PL_EQ_TX_POSTCUR_10x000000024432rwNormal read/write0x00000000Tx POST-Cursor for Preset1
PL_EQ_TX_POSTCUR_20x000000024832rwNormal read/write0x00000000Tx POST-Cursor for Preset2
PL_EQ_TX_POSTCUR_30x000000024C32rwNormal read/write0x00000000Tx POST-Cursor for Preset3
PL_EQ_TX_POSTCUR_40x000000025032rwNormal read/write0x00000000Tx POST-Cursor for Preset4
PL_EQ_TX_POSTCUR_50x000000025432rwNormal read/write0x00000000Tx POST-Cursor for Preset5
PL_EQ_TX_POSTCUR_60x000000025832rwNormal read/write0x00000000Tx POST-Cursor for Preset6
PL_EQ_TX_POSTCUR_70x000000025C32rwNormal read/write0x00000000Tx POST-Cursor for Preset7
PL_EQ_TX_POSTCUR_80x000000026032rwNormal read/write0x00000000Tx POST-Cursor for Preset8
PL_EQ_TX_POSTCUR_90x000000026432rwNormal read/write0x00000000Tx POST-Cursor for Preset8
PL_EQ_TX_POSTCUR_A0x000000026832rwNormal read/write0x00000000Tx POST-Cursor for PresetA
PL_EQ_TX_POSTCUR_B0x000000026C32rwNormal read/write0x00000000Tx POST-Cursor for PresetB
PL_EQ_TX_POSTCUR_C0x000000027032rwNormal read/write0x00000000Tx POST-Cursor for PresetC
PL_EQ_TX_POSTCUR_D0x000000027432rwNormal read/write0x00000000Tx POST-Cursor for PresetD
PL_EQ_TX_POSTCUR_E0x000000027832rwNormal read/write0x00000000Tx POST-Cursor for PresetE
PL_EQ_TX_POSTCUR_F0x000000027C32rwNormal read/write0x00000000Tx POST-Cursor for PresetF
PL_EQ_TX_MAINCUR_00x000000028032rwNormal read/write0x00000000Tx MAIN-Cursor for Preset0
PL_EQ_TX_MAINCUR_10x000000028432rwNormal read/write0x00000000Tx MAIN-Cursor for Preset1
PL_EQ_TX_MAINCUR_20x000000028832rwNormal read/write0x00000000Tx MAIN-Cursor for Preset2
PL_EQ_TX_MAINCUR_30x000000028C32rwNormal read/write0x00000000Tx MAIN-Cursor for Preset3
PL_EQ_TX_MAINCUR_40x000000029032rwNormal read/write0x00000000Tx MAIN-Cursor for Preset4
PL_EQ_TX_MAINCUR_50x000000029432rwNormal read/write0x00000000Tx MAIN-Cursor for Preset5
PL_EQ_TX_MAINCUR_60x000000029832rwNormal read/write0x00000000Tx MAIN-Cursor for Preset6
PL_EQ_TX_MAINCUR_70x000000029C32rwNormal read/write0x00000000Tx MAIN-Cursor for Preset7
PL_EQ_TX_MAINCUR_80x00000002A032rwNormal read/write0x00000000Tx MAIN-Cursor for Preset8
PL_EQ_TX_MAINCUR_90x00000002A432rwNormal read/write0x00000000Tx MAIN-Cursor for Preset9
PL_EQ_TX_MAINCUR_A0x00000002A832rwNormal read/write0x00000000Tx MAIN-Cursor for PresetA
PL_EQ_TX_MAINCUR_B0x00000002AC32rwNormal read/write0x00000000Tx MAIN-Cursor for PresetB
PL_EQ_TX_MAINCUR_C0x00000002B032rwNormal read/write0x00000000Tx MAIN-Cursor for PresetC
PL_EQ_TX_MAINCUR_D0x00000002B432rwNormal read/write0x00000000Tx MAIN-Cursor for PresetD
PL_EQ_TX_MAINCUR_E0x00000002B832rwNormal read/write0x00000000Tx MAIN-Cursor for PresetE
PL_EQ_TX_MAINCUR_F0x00000002BC32rwNormal read/write0x00000000Tx MAIN-Cursor for PresetF
PL_EQ_LF0x00000002C032rwNormal read/write0x00000000Xilinx GT EQ Low Frequency
PL_EQ_FS0x00000002C432rwNormal read/write0x00000000Xilinx GT EQ Full Swing
PL_EQ_LP_TXPRESET0x00000002C832rwNormal read/write0x00000000Preset Proposal to be sent to link partner during Phase2/3 that is Xilinx implemementation specific (Main).
PL_EQ_LP_TXPRESET20x00000002CC32rwNormal read/write0x00000000Preset Proposal to be sent to link partner during Phase2/3 that is Xilinx implemementation specific (Backup).
PL_EQ_RX_ADAPT_TIMER0x00000002D032rwNormal read/write0x00000000Rx Adapatation Time in Phase 2/3. This is the wait time for GTY Rx to adapt during Phase 2/3.
PL_EQ_RX_ADAPT_TIMER_SIM0x00000002D432rwNormal read/write0x00000000Rx Adapatation Time in Phase 2/3 in simulation. This is the wait time for GTY Rx to adapt during Phase 2/3.
PL_EQ_RX_ADAPT_SIM_ENABLE0x00000002D832rwNormal read/write0x00000000Enables using
PL_EQ_RX_ADAPT_TIMER_SIM when TRUE, else PL_EQ_RX_ADAPT_TIMER is used.
PL_SELF_TRAIN0x00000002DC32rwNormal read/write0x00000000Enabled Loopback Self Link Up when PL_UPSTREAM_FACING = FALSE. To be used by GOQ for Production Test.
PL_ENABLE_CCIX_EDR0x00000002E032rwNormal read/write0x00000000Enable CCIX EDR mode.
PL_ENABLE_CCIX_EDR_REACH_MODE0x00000002E432rwNormal read/write0x00000000Enable CCIX EDR
Reach Mode.PL_ENABLE_CCIX_EDR must be TRUE
00b = Short Reach Capable only
01b = Long Reach Capable only
10b = Short & Long Reach Capable
11b = Reserved
PL_RECALIBRATION_NEEDED_ON_ESM_RATE01_PROGRAMMING_CHANGE0x00000002E832rwNormal read/write0x00000000Physical requires recalibration if ESM Control Register, ESM Data Rate0/1 fields are changed. If TRUE, else not re-calibration is needed if FALSE.
PL_CCIX_ESM_CALIBRATION_TIMEOUT0x00000002EC32rwNormal read/write0x00000000CCIX ESM Calibration Timeout. PL_ENABLE_CCIX_EDR must be TRUE.
000b = 10 us
001b = 50 us
010b = 100 us
011b = 500 us
100b = 1 ms
101b = 5 ms
110b = 10 ms
111b = 50 ms
PL_CCIX_ESM_EXTENDED_EQ_TIMEOUT0x00000002F032rwNormal read/write0x00000000ESM Extended Equalization Phase2/3 Timeout. Used to initialize Upstream Ports ESM Control Register, ESM Extended Equalization Phase2 Timeout field or Downstream Ports ESM Control Register, ESM Extended Equalization Phase3 Timeout field. Initialized fields are used to control Phase2 Timeout to Recovery.Speed (Upstream Port) or Phase3 Timeout to Recovery.Speed (Downstream Port). PL_ENABLE_CCIX_EDR must be TRUE.
000b = 24 ms / 32 ms
001b = 50 ms / 58 ms
010b = 100 ms / 108 ms
011b = 200 ms / 208 ms
100b = 400 ms / 408 ms
101b = 600 ms / 608 ms
Other Encodings = Reserved
PL_LANE0_CCIX_EDR_EQ_CONTROL0x00000002F432rwNormal read/write0x00000000Lane#0 CCIX EDR Equalization Control Register:
Bit[3:0] - Downstream Port 20G Transmitter Preset
Bit[11:8] - Upstream Port 20G Transmitter Preset
Bit[19:16] - Downstream Port 25G Transmitter Preset
Bit[27:24] - Upstream Port 25G Transmitter Preset
PL_LANE1_CCIX_EDR_EQ_CONTROL0x00000002F832rwNormal read/write0x00000000Lane#1 CCIX EDR Equalization Control Register:
Bit[3:0] - Downstream Port 20G Transmitter Preset
Bit[11:8] - Upstream Port 20G Transmitter Preset
Bit[19:16] - Downstream Port 25G Transmitter Preset
Bit[27:24] - Upstream Port 25G Transmitter Preset
PL_LANE2_CCIX_EDR_EQ_CONTROL0x00000002FC32rwNormal read/write0x00000000Lane#2 CCIX EDR Equalization Control Register:
Bit[3:0] - Downstream Port 20G Transmitter Preset
Bit[11:8] - Upstream Port 20G Transmitter Preset
Bit[19:16] - Downstream Port 25G Transmitter Preset
Bit[27:24] - Upstream Port 25G Transmitter Preset
PL_LANE3_CCIX_EDR_EQ_CONTROL0x000000030032rwNormal read/write0x00000000Lane#3 CCIX EDR Equalization Control Register:
Bit[3:0] - Downstream Port 20G Transmitter Preset
Bit[11:8] - Upstream Port 20G Transmitter Preset
Bit[19:16] - Downstream Port 25G Transmitter Preset
Bit[27:24] - Upstream Port 25G Transmitter Preset
PL_LANE4_CCIX_EDR_EQ_CONTROL0x000000030432rwNormal read/write0x00000000Lane#4 CCIX EDR Equalization Control Register:
Bit[3:0] - Downstream Port 20G Transmitter Preset
Bit[11:8] - Upstream Port 20G Transmitter Preset
Bit[19:16] - Downstream Port 25G Transmitter Preset
Bit[27:24] - Upstream Port 25G Transmitter Preset
PL_LANE5_CCIX_EDR_EQ_CONTROL0x000000030832rwNormal read/write0x00000000Lane#5 CCIX EDR Equalization Control Register:
Bit[3:0] - Downstream Port 20G Transmitter Preset
Bit[11:8] - Upstream Port 20G Transmitter Preset
Bit[19:16] - Downstream Port 25G Transmitter Preset
Bit[27:24] - Upstream Port 25G Transmitter Preset
PL_LANE6_CCIX_EDR_EQ_CONTROL0x000000030C32rwNormal read/write0x00000000Lane#6 CCIX EDR Equalization Control Register:
Bit[3:0] - Downstream Port 20G Transmitter Preset
Bit[11:8] - Upstream Port 20G Transmitter Preset
Bit[19:16] - Downstream Port 25G Transmitter Preset
Bit[27:24] - Upstream Port 25G Transmitter Preset
PL_LANE7_CCIX_EDR_EQ_CONTROL0x000000031032rwNormal read/write0x00000000Lane#7 CCIX EDR Equalization Control Register:
Bit[3:0] - Downstream Port 20G Transmitter Preset
Bit[11:8] - Upstream Port 20G Transmitter Preset
Bit[19:16] - Downstream Port 25G Transmitter Preset
Bit[27:24] - Upstream Port 25G Transmitter Preset
PL_EQ_DEFAULT_CCIX_EDR_TX_PRESET0x000000031432rwNormal read/write0x00000000Default CCIX EDR Tx Preset: This value is used in transmitted TS1s by Endpoint in EQ Phase0,if no EQ TS2 are receied during EQ Phase0. bits[3:0] are for 20G operation, bits[7:4] are for 25G operation. Others bits are reserved.
PL_USER_SPARE0x000000031832rwNormal read/write0x00000000bit 0: 1b: In Polling.Active, allow transition to Polling.Cfg even if all lanes that detected Receiver, did not, exit Electrical Idle. 0b: Spec compliant behavior.
Bit 1: 1b: In Recovery.Speed, Disable transition to Detect if phy_status not asserted in 1ms. 0b: Spec Compliant behavior.
Bit 2: 1b: For Upstream Port only. At Gen3 speed in Recovery RcvrCfg, when changing speed to Gen4, will transmit 8GT EQ TS2 Ordered Sets. 0b: TS2 are transmitted
Bit 3: 1b: For Upstream Port only. In Rec.RcvrCfg Tx TS2 Symbol 4 bit 6 (incrrectly) reflects Rx de-emphasis (Symbol4 bit 6) in TS2. 0b:
In Rec.RcvrCfg Tx TS2 Symbol 4 bit 6 is set to 0b.
Bit 4: 1b: Enables Gen4 (pre 0.7 spec) new EIEOS (both Rx, Tx). 0b: Original 8G EIEOS behavior on Tx & Rx.
Bit 5(chicken bit): 1b: Enabled highest common supported speed based decision making in R.Speed.
Bit 6(chicken bit): set to zero to increase the RX deskew FIFO depth from 8-12 entries, cahnge back to 8 entries when set to one.
Bit 7 (chicken bit): When set to zero will sanple sync header only when start block is high, when set to zero sync header is passed on as is from PIPE interface.
Bit 8 (chicken bit): When set to zero will reset the cnt_ff in osdcommon on ltssm state transitions.
Bit 9 (chicken bit): When set to zero polarity reset on linkdown ltssm state transitions.
Bit 10: Reserved
Bit 11: Chicken bit for stop new request fix
Bit 12: Chicken bit for Gen2 deemph restore
Bit 11: Stop new request fix
Bit 13: Chicken bit used for Need to exit for ECO PCIe V2.0(SI# 948565)
Bit 14: Chicken bit for quiese garantee bit ECO for PCIe V2.0
(SI# 948564)
Bit 15: Chicken bit for skp rcvd all changes to skp rcvd any lane ECO Pcie V2.0 (SI# 948565)
PL_USER_SPARE20x000000031C32rwNormal read/write0x00000000PL User Spare2: Bit 0: Used in recovery.rcvrlock to add defualt values to link auto bandwidth spec var.
Bit 1: Used in override deemphasis value to config from pl.
Bit 2: Used in recovery_rcvrlock to disable DSP extended sync check of 1024 TS OS in recovery_rcvrlock.
Bit 3: Used in Rx Margin to override the max num lanes allowed for Rx Margin.
Bit [8 - 4]: Max Num lanes value, when override is set.
Bit 9: Used to disable passid, so in the TLP length check passid format type is not checked.
PL_USER_SPARE30x000000032032rwNormal read/write0x00000000PL User Spare3:
LL_ACK_TIMEOUT_EN0x000000032432rwNormal read/write0x00000000Enables the Ack/Nak Latency Timer to use the user-defined LL_ACK_TIMEOUT value (or combined with the built-in value, depending on LL_ACK_TIMEOUT_FUNC). If FALSE, the built-in value is used.
LL_ACK_TIMEOUT0x000000032832rwNormal read/write0x00000000Sets a user-defined timeout for the Ack/Nak Latency Timer to force any pending ACK or NAK DLLPs to be transmitted; refer to LL_ACK_TIMEOUT_EN and LL_ACK_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is 4ns at GEN1 speeds, 2ns at GEN2, 1ns at GEN3 and 0.5ns at GEN4 (current speed)
LL_ACK_TIMEOUT_FUNC0x000000032C32rwNormal read/write0x00000000Defines how LL_ACK_TIMEOUT is to be used, if enabled with LL_ACK_TIMEOUT_EN (otherwise, this is not used).
0 = No Effect
1 = Add LL_ACK_TIMEOUT to the built-in table value.
2 = Subtract LL_ACK_TIMEOUT from the built-in table value. Here LL_ACK_TIMEOUT
value should follow the following rules: a) For any Width, Gen1/2/3/4 speed iff MPS > 512B: Allowed Range is 1 <= RANGE <= 64d
b) For any Width, Gen1/2/3/4 speed iff MPS <= 512B: Allowed Range is 1 <= RANGE <= 32d
LL_REPLAY_TIMEOUT_EN0x000000033032rwNormal read/write0x00000000Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.
LL_REPLAY_TIMEOUT0x000000033432rwNormal read/write0x00000000Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is 4ns at GEN1 speeds, 2ns at GEN2, 1ns at GEN3 and 0.5ns at GEN4 (current speed)
LL_REPLAY_TIMEOUT_FUNC0x000000033832rwNormal read/write0x00000000Defines how LL_REPLAY_TIMEOUT is to be used, if enabled with LL_REPLAY_TIMEOUT_EN (otherwise, this is not used).
0 = No Effect
1 = Add LL_REPLAY_TIMEOUT to the built-in table value.
2 = Subtract
LL_REPLAY_TIMEOUT from the built-in table value.
Here LL_REPLAY_TIMEOUT
value should follow the following rules: a) For any Width, Gen1/2/3/4 speed iff MPS > 512B: Allowed Range is 1 <= RANGE <= 64d
b) For any Width, Gen1/2/3/4 speed iff MPS <= 512B: Allowed Range is 1 <= RANGE <= 32d
LL_REPLAY_TO_RAM_PIPELINE0x000000033C32rwNormal read/write0x00000000To Replay RAM
Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on Hard Block to BRAM path (addr, wen, ren, wdata). FALSE indicates that there is no pipeline.
LL_REPLAY_FROM_RAM_PIPELINE0x000000034032rwNormal read/write0x00000000From Replay RAM Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on BRAM to Hard Block path (rdata). FALSE indicates that there is no pipeline.
LL_DISABLE_SCHED_TX_NAK0x000000034432rwNormal read/write0x00000000Disable Scheduling on NAK: When TRUE, all actions related to NAK generation will be
performed, except for NAK scehduled for transmission. When FALSE, for spec compliant behavior.
LL_TX_TLP_PARITY_CHK0x000000034832rwNormal read/write0x00000000Link Layer Parity Check in Tx Path: When TRUE, checks and reports parity failure on on parity information presented on ll2lm_s_axis_tx_tparity[31:0]. No check/reporting if FALSE. Used in conjunction with AXISTEN_IF_TX_PARITY_EN.
LL_RX_TLP_PARITY_GEN0x000000034C32rwNormal read/write0x00000000Link Layer Parity Generation in Rx Path: When TRUE, LL will compute and drive
parity on on ll2lm_m_axis_rx_tparity[31:0]. When FALSE,
ll2lm_m_axis_rx_tparity[31:0] will be driven to 32b0. Used in conjunction with AXISTEN_IF_RX_PARITY_EN.
LL_UFC_ARBITER_ENABLE0x000000035032rwNormal read/write0x00000000MultiVC UCF Arbiter Enable. When TRUE enabled, else disabled. Required to be TRUE when CCIX is enabled.
CFG_PRIVATE_SPC0x000000035432rwNormal read/write0x00000000When TRUE, enables Replay and Ack Timeouts come from private configuration space registers
LL_FEATURE_EN_DLLP_EXCHANGE0x000000035832rwNormal read/write0x00000000Link Layer Feature Enable DLLP Exchange: When TRUE enables exchange of Feature DLLP
LL_FEATURE_EN_FC_SCALING0x000000035C32rwNormal read/write0x00000000Link Layer Feature Enable Flow Control Scaling: When TRUE, FC Scaling feature is enabled. When FALSE, FC Scaling feature is disabled.
LL_FEATURE_EN_FC_SCALING_SCALE_FACTOR_40x000000036032rwNormal read/write0x00000000Link Layer Feature Enable Flow Control Scaling Scale Factor 4: When TRUE, FC Scaling Scale Factor is 4 is enabled. When FALSE, FC Scaling Scale Factor is 1.
LL_REPLAY_TIMER40_ENABLE0x000000036432rwNormal read/write0x00000000Enable Replay Timer 4.0 Spec Timeout: When TRUE, enables the PCIe 4.0 Spec v0.7 replay timer.
When FALSE, the replay timer timeouts are based on the ack timeout values (Pre-4.0 v0.7 Spec and 3.1 Spec replay timer timeouts).
LL_TX_STALL_ON_ASPM_L1_ENTRY_DISABLE0x000000036832rwNormal read/write0x00000000Stall Tx Traffic on Entry into ASPM L1 Disable: When TRUE, Disabled the behehavior, where DLL Stall the TL on entry into ASPM L1
LL_TX_STALL_ON_PPM_L1_ENTRY_DISABLE0x000000036C32rwNormal read/write0x00000000Stall Tx Traffic on Entry into PPM L1 Disable: When TRUE, Disabled the behehavior, where DLL Stall the TL on entry into PPM L1
LL_TX_PARITY_CHECK_CHANGE_DISABLE0x000000037032rwNormal read/write0x00000000Parity Check Change Disable: When TRUE, Parity Check fix is disabled
LL_USER_SPARE0x000000037432rwNormal read/write0x00000000LL ECO Spare Bits (set to 16h0008)
bit 0
: 1b: Disables ACK in same beat as end of TLP.
0b: Enables feature
bit 1
: 1b: Disables LL ECO 2 (framing).
0b: Enables ECO 2 (framing)
bit 2
: 1b: Disables LL ECO 1 (for tlp).
0b: Enables ECO 1 (for tlp)
bit 3
: 1b: Disables LL ECO 1 (for updatefc).
0b: Enables ECO 1 (for updatefc)
bit 4
: 1b: Disables LL ECO 1 (for ack).
0b: Enables ECO 1 (for ack)
bit 5
: 1b: Disables Reporting of ECC Uncorrectable Errors.
0b: Enables reporting
bit 6
: 1b: Disables Reporting of ECC Correctable Errors.
0b: Enables reporting
bit 7
: 1b: Disables Reporting of Tx Parity Check Failure.
0b: Enables reporting
bits15:5: Reserved
IS_SWITCH_PORT0x000000037832rwNormal read/write0x00000000Switch Port Control: For Built-in Switch Upstream Port: When set to TRUE and PL_UPSTREAM_FACING must be TRUE. For Built-in Switch Downstream Port: When set to TRUE and PL_UPSTREAM_FACING must be FALSE. TL_PF_ENABLE_REG must be set to 00b and SRIOV_CAP_ENABLE must be set to FALSE.
TL_PF_ENABLE_REG0x000000038032rwNormal read/write0x00000000Root (RC) has 1 function and this register must be set to 00b.
EP Mode has multi-function support:
Function #s 1,2,3 Enable:
00b = Functions #s 1,2,3 Disabled.
01b = Functions #1 Enabled.
10b = Functions #s 1,2 Enabled.
11b = Functions #s 1,2,3 Enabled.
TL_CREDITS_CD0x000000038432rwNormal read/write0x00000000Receiver Credit Limit for Completion Data. Unit is credits. Supported values are:
0, 700H, 7FFH, F10H, 781H, or 7C0H
TL_CREDITS_CD_VC10x000000038832rwNormal read/write0x00000000Receiver Credit Limit for Completion Data for VC1. Unit is credits. Supported values are:
must be set to 000H (infinite).
TL_CREDITS_CH0x000000038C32rwNormal read/write0x00000000Receiver Credit Limit for Completion Header. Unit is number of TLPs. Supported values are:
0, 40H, 7FH or F0H
TL_CREDITS_CH_VC10x000000039032rwNormal read/write0x00000000Receiver Credit Limit for Completion Header for VC1. Unit is number of TLPs. Supported values are:
must be set to 00H (infinite).
TL_COMPLETION_RAM_SIZE0x000000039432rwNormal read/write0x00000000Receive Completion RAM Size:
00b - 8,192 Bytes
01b - 16,384 Bytes
10b - 32,768 Bytes.
11b - 65,536 Bytes
TL_COMPLETION_RAM_NUM_TLPS0x000000039832rwNormal read/write0x00000000Receive Completion RAM Max.Number of TLP Capacity:
00b - 64D
01b - 128D
10b - 256D
11b - 1024D
TL_CREDITS_NPD0x000000039C32rwNormal read/write0x00000000Credit Limit for Non Posted Data.
Unit is credits. Supported values are:
40H
TL_CREDITS_NPD_VC10x00000003A032rwNormal read/write0x00000000Credit Limit for Non Posted Data for VC1.
Unit is credits. Supported values are: 00H
TL_NP_FIFO_NUM_TLPS0x00000003A432rwNormal read/write0x00000000Maximum number of TLP headers that can be stored in the Non-Posted Receive FIFO.
0 = 64
1 = 127
TL_CREDITS_NPH0x00000003A832rwNormal read/write0x00000000Receiver Credit Limit for Non Posted Header.
Unit is number of TLPs. Supported values are:
20H when TL_NP_FIFO_NUM_TLPS = 0b, 7FH when TL_NP_FIFO_NUM_TLPS = 1b
TL_CREDITS_NPH_VC10x00000003AC32rwNormal read/write0x00000000Receiver Credit Limit for Non Posted Header for VC1.
Unit is number of TLPs. Supported values are:
01H = 01D TLPs
TL_CREDITS_PD0x00000003B032rwNormal read/write0x00000000Receiver Credit Limit for
Posted Data.
Unit is credits. Supported values are:
3E0H when TL_POSTED_RAM_SIZE = 0b, 781H when TL_POSTED_RAM_SIZE = 1b
TL_CREDITS_PD_VC10x00000003B432rwNormal read/write0x00000000Receiver Credit Limit for
Posted Data for VC1.
Unit is credits. Supported values are:
3E0H = 992D - 15,872B (TL_RX_CCIX_FIFO_RAM_SIZE = 1b)
TL_CREDITS_PH0x00000003B832rwNormal read/write0x00000000Receiver Credit Limit for
Posted Header. Unit is number of TLPs. Supported values are:
20H when TL_POSTED_RAM_SIZE = 0b, 7FH when TL_POSTED_RAM_SIZE = 1b
TL_CREDITS_PH_VC10x00000003BC32rwNormal read/write0x00000000Receiver Credit Limit for
Posted Header for VC1. Unit is number of TLPs. Supported values are:
40H=64D TLPs
TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE0x00000003C032rwNormal read/write0x00000000TL To Completion RAM Write Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on waddr, wdata, wen. FALSE indicates that there is no pipeline. Must be equal to TL_RX_COMPLETION_TO_RAM_READ_PIPELINE selection.
TL_RX_COMPLETION_TO_RAM_READ_PIPELINE0x00000003C432rwNormal read/write0x00000000TL To Completion RAM Read Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on raddr, ren. FALSE indicates that there is no pipeline. Must be equal to TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE selection.
TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE0x00000003C832rwNormal read/write0x00000000Completion RAM to TL Read Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on rdata. FALSE indicates that there is no pipeline.
TL_POSTED_RAM_SIZE0x00000003CC32rwNormal read/write0x00000000Receive Posted RAM Size:
0b - 16KB
1b - 32KB
TL_RX_POSTED_TO_RAM_WRITE_PIPELINE0x00000003D032rwNormal read/write0x00000000TL
to Posted RAM Write Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on waddr, wdata, wen. FALSE indicates that there is no pipeline. Must be equal to TL_RX_POSTED_TO_RAM_READ_PIPELINE selection.
TL_RX_POSTED_TO_RAM_READ_PIPELINE0x00000003D432rwNormal read/write0x00000000TL
to Posted RAM Read Pipeline:
If TRUE indicates presence of a external CLB flip-flop pipeline stage on raddr, ren. FALSE indicates that there is no pipeline. Must be equal to TL_RX_POSTED_TO_RAM_WRITE_PIPELINE selection.
TL_RX_POSTED_FROM_RAM_READ_PIPELINE0x00000003D832rwNormal read/write0x00000000Posted RAM To TL Read Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on rdata. FALSE indicates that there is no pipeline.
TL_TX_MUX_STRICT_PRIORITY0x00000003DC32rwNormal read/write0x00000000Transaction Tx mux arbitration scheme between RQ and CC traffic. If TRUE selects strict priority. If FALSE selects round robin priority.
TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT0x00000003E832rwNormal read/write0x00000000Transaction Tx Update FC Interval TLP Count: Indicates the minimum number of Posted, Non-Posted or Completion TLPs that must be received before an update FC is scheduled for transmission. Once the required number of TLPs are received, an Update FC is scheduled for transmission and count is reset to the value programmed in TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT[4:0] and
the internal timer is reset to start counting down from the value indicated by TL_FC_UPDATE_MIN_INTERVAL_TIME[4:0] (if enabled). Programming 0d indicates that the feature is disabled.
TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC10x00000003EC32rwNormal read/write0x00000000Transaction Tx Update FC Interval TLP Count for VC1: Indicates the minimum number of Posted, Non-Posted or Completion TLPs that must be received before an update FC is scheduled for transmission. Once the required number of TLPs are received, an Update FC is scheduled for transmission and count is reset to the value programmed in TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT[4:0] and
the internal timer is reset to start counting down from the value indicated by TL_FC_UPDATE_MIN_INTERVAL_TIME[4:0] (if enabled). Programming 0d indicates that the feature is disabled.
TL_FC_UPDATE_MIN_INTERVAL_TIME0x00000003F032rwNormal read/write0x00000000Transaction Tx Update FC Interval Timer: Expressed in units of 1us elapsed time and tracked independently for Posted, Non-Posted and Completion (if applicable) credit queues. An update FC is scehdule for transmission only
after time indicated by valuye of TL_FC_UPDATE_MIN_INTERVAL_TIME[4:0] has elapsed after receeption of a TLP, and number of TLPs indicated by TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT[4:0] have not been received. Once an Update FC is scheduled for transimission, the internal timer is reset to start counting down from the value indicated by TL_FC_UPDATE_MIN_INTERVAL_TIME[4:0] and received TLP count is reset to start counting down from value indicated by TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT[4:0] (if enabled). Value of 0d indicates that the feature is disabled.
TL_FC_UPDATE_MIN_INTERVAL_TIME_VC10x00000003F432rwNormal read/write0x00000000Transaction Tx Update FC Interval Timer for VC1: Expressed in units of 1us elapsed time and tracked independently for Posted, Non-Posted and Completion (if applicable) credit queues. An update FC is scehdule for transmission only
after time indicated by valuye of TL_FC_UPDATE_MIN_INTERVAL_TIME[4:0] has elapsed after receeption of a TLP, and number of TLPs indicated by TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT[4:0] have not been received. Once an Update FC is scheduled for transimission, the internal timer is reset to start counting down from the value indicated by TL_FC_UPDATE_MIN_INTERVAL_TIME[4:0] and received TLP count is reset to start counting down from value indicated by TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT[4:0] (if enabled). Value of 0d indicates that the feature is disabled.
TL_FEATURE_ENABLE_FC_SCALING0x00000003F832rwNormal read/write0x00000000Transaction Layer Flow Control Scaling: When TRUE, FC Scaling feature is enabled. When FALSE, FC Scaling feature is disabled.
TL_RX_CCIX_FIFO_RAM_SIZE0x00000003FC32rwNormal read/write0x00000000Receive Rx CCIX FIFO RAM Size:
0b - Reserved
1b - 16KB (64 TLPs)
TL_RX_CCIX_FIFO_TO_RAM_WRITE_PIPELINE0x000000040032rwNormal read/write0x00000000TL
to
RX CCIX FIFO RAM Write Pipeline: If TRUE indicates presence of a external flip-flop pipeline stage on waddr, wdata, wen. FALSE indicates that there is no pipeline. Must be equal to TL_RX_CCIX_FIFO_TO_RAM_READ_PIPELINE selection.
TL_RX_CCIX_FIFO_TO_RAM_READ_PIPELINE0x000000040432rwNormal read/write0x00000000TL
to RX CCIX FIFO RAM Read Pipeline:
If TRUE indicates presence of a external
flip-flop pipeline stage on raddr, ren. FALSE indicates that there is no pipeline. Must be equal to TL_RX_CCIX_FIFO_TO_RAM_WRITE_PIPELINE selection.
TL_RX_CCIX_FIFO_FROM_RAM_READ_PIPELINE0x000000040832rwNormal read/write0x00000000RX CCIX FIFO RAM To TL Read Pipeline: If TRUE indicates presence of a external = flip-flop pipeline stage on rdata. FALSE indicates that there is no pipeline.
TL_DISABLE_RX_FLOW_CTL0x000000040C32rwNormal read/write0x00000000Disable Rx Flow Control: When set to 1b, disables internal flow control credit return mechanism, and enables, the tl_rx_{posted,nonposted,completion}_*_released_* (user_spare_in interface). Sould be set to 0b for normal operation.
TL_USER_SPARE0x000000041032rwNormal read/write0x00000000TL Spare Bits for future Gen4 related new features:
bit 0 - disable_overflow_reporting Enable = 1b, Disable = 0b.
PFx_CLASS_CODE_00x000000041432rwNormal read/write0x00000000Class Code: Code identifying basic function, subclass and applicable programming interface.
Transferred to the Class Code, Sub-Class Code and Programming Interface. VFs must return the same Class code as the corresponding PF.
PFx_CLASS_CODE_10x000000041832rwNormal read/write0x00000000Class Code: Code identifying basic function, subclass and applicable programming interface.
Transferred to the Class Code, Sub-Class Code and Programming Interface. VFs must return the same Class code as the corresponding PF.
PFx_CLASS_CODE_20x000000041C32rwNormal read/write0x00000000Class Code: Code identifying basic function, subclass and applicable programming interface.
Transferred to the Class Code, Sub-Class Code and Programming Interface. VFs must return the same Class code as the corresponding PF.
PFx_CLASS_CODE_30x000000042032rwNormal read/write0x00000000Class Code: Code identifying basic function, subclass and applicable programming interface.
Transferred to the Class Code, Sub-Class Code and Programming Interface. VFs must return the same Class code as the corresponding PF.
PFx_INTERRUPT_PIN_00x000000042432rwNormal read/write0x00000000Interrupt Pin Register: Indicates mapping for legacy interrupt messages.
Valid values are 1 INTA, 2 INTB, 3 INTC, 4 INTD.
Zero indicates no legacy interrupt messages used. Doesnot apply to VFs.
PFx_INTERRUPT_PIN_10x000000042832rwNormal read/write0x00000000Interrupt Pin Register: Indicates mapping for legacy interrupt messages.
Valid values are 1 INTA, 2 INTB, 3 INTC, 4 INTD.
Zero indicates no legacy interrupt messages used. Doesnot apply to VFs.
PFx_INTERRUPT_PIN_20x000000042C32rwNormal read/write0x00000000Interrupt Pin Register: Indicates mapping for legacy interrupt messages.
Valid values are 1 INTA, 2 INTB, 3 INTC, 4 INTD.
Zero indicates no legacy interrupt messages used. Doesnot apply to VFs.
PFx_INTERRUPT_PIN_30x000000043032rwNormal read/write0x00000000Interrupt Pin Register: Indicates mapping for legacy interrupt messages.
Valid values are 1 INTA, 2 INTB, 3 INTC, 4 INTD.
Zero indicates no legacy interrupt messages used. Doesnot apply to VFs.
PFx_CAPABILITY_POINTER_00x000000043432rwNormal read/write0x00000000Capability Pointer: Next capability pointer at 34H in each PF.
PFx_CAPABILITY_POINTER_10x000000043832rwNormal read/write0x00000000Capability Pointer: Next capability pointer at 34H in each PF.
PFx_CAPABILITY_POINTER_20x000000043C32rwNormal read/write0x00000000Capability Pointer: Next capability pointer at 34H in each PF.
PFx_CAPABILITY_POINTER_30x000000044032rwNormal read/write0x00000000Capability Pointer: Next capability pointer at 34H in each PF.
VF0_CAPABILITY_POINTER0x000000044432rwNormal read/write0x00000000Capability Pointer: Next capability pointer at 34H for all VFs
LEGACY_CFG_EXTEND_INTERFACE_ENABLE0x000000044832rwNormal read/write0x00000000Configuration Legacy Space Extend Interface Enable: When TRUE, all received Configuration Type0 Transactions, in register address range 0xB0-0xBF, for every enabled function, will be steered to the CFGEXT interface.
EXTENDED_CFG_EXTEND_INTERFACE_ENABLE0x000000044C32rwNormal read/write0x00000000Configuration Extended Space Extend Interface Enable: When TRUE, all received Configuration Type0 Transactions, in the register address range 0x400-0x4FF, for every enabled function, will be steered
to the CFGEXT interface.
TL2CFG_IF_PARITY_CHK0x000000045032rwNormal read/write0x00000000Data Path Parity Check on TL2CFG
TRUE -- parity check is enabled
FALSE --
parity check is disabled
HEADER_TYPE_OVERRIDE0x000000045432rwNormal read/write0x00000000Header Type Override
TRUE - Header Type field bit0 will set to 0b.
FALSE - For Root Port and Switches, Header Type bit0 will be set to 1b
CFG_SPEC_4_00x000000045832rwNormal read/write0x00000000Enable 4.0 Specification in the Cfg Space. When TRUE.
PFx_BAR0_CONTROL_00x000000045C32rwNormal read/write0x00000000BAR0 Control - Specifies the configuration of BAR 0.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_BAR0_CONTROL_10x000000046032rwNormal read/write0x00000000BAR0 Control - Specifies the configuration of BAR 0.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_BAR0_CONTROL_20x000000046432rwNormal read/write0x00000000BAR0 Control - Specifies the configuration of BAR 0.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_BAR0_CONTROL_30x000000046832rwNormal read/write0x00000000BAR0 Control - Specifies the configuration of BAR 0.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_BAR0_APERTURE_SIZE_00x000000046C32rwNormal read/write0x00000000BAR0 Aperture: Specifies the aperture of BAR 0.
[The 32-bit BAR 0 or 64-bit BAR 0-1.]
For Endpoint Mode the encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
For Root Port Mode (PF0 only), the encodings are:
000000 = 4 bytes
000001 = 8 bytes
000010 = 16 bytes
000011 = 32 bytes
000100 = 84 bytes
000101 = 128 bytes
000110 = 256 bytes
000111 = 512 bytes
001000 = 1 Kbytes
001001 = 2 Kbytes
001010 = 4 Kbytes
001011 = 8 Kbytes
001100 = 16 Kbytes
001101 = 32 Kbytes
001110 = 64 Kbytes
001111 = 128 Kbytes
010000 = 256 Kbytes
010001 = 512 Kbytes
010010 = 1 Mbytes
010011 = 2 Mbytes
010100 = 4 Mbytes
010101 = 8 Mbytes
010110 = 16 Mbytes
010111 = 32 Mbytes
011000 = 64 Mbytes
011001 = 128 Mbytes
011010 = 256 Mbytes
011011 = 512 Mbytes
011100 = 1 Gbytes
011101 = 2 Gbytes
011110 = 4 Gbytes
011111 = 8 Gbytes
100000 = 16 Gbytes
100001 = 32 Gbytes
100010 = 64 Gbytes
100011 = 128 Gbytes
100100 = 256 Gbytes
PFx_BAR0_APERTURE_SIZE_10x000000047032rwNormal read/write0x00000000BAR0 Aperture: Specifies the aperture of BAR 0.
[The 32-bit BAR 0 or 64-bit BAR 0-1.]
For Endpoint Mode the encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
For Root Port Mode (PF0 only), the encodings are:
000000 = 4 bytes
000001 = 8 bytes
000010 = 16 bytes
000011 = 32 bytes
000100 = 84 bytes
000101 = 128 bytes
000110 = 256 bytes
000111 = 512 bytes
001000 = 1 Kbytes
001001 = 2 Kbytes
001010 = 4 Kbytes
001011 = 8 Kbytes
001100 = 16 Kbytes
001101 = 32 Kbytes
001110 = 64 Kbytes
001111 = 128 Kbytes
010000 = 256 Kbytes
010001 = 512 Kbytes
010010 = 1 Mbytes
010011 = 2 Mbytes
010100 = 4 Mbytes
010101 = 8 Mbytes
010110 = 16 Mbytes
010111 = 32 Mbytes
011000 = 64 Mbytes
011001 = 128 Mbytes
011010 = 256 Mbytes
011011 = 512 Mbytes
011100 = 1 Gbytes
011101 = 2 Gbytes
011110 = 4 Gbytes
011111 = 8 Gbytes
100000 = 16 Gbytes
100001 = 32 Gbytes
100010 = 64 Gbytes
100011 = 128 Gbytes
100100 = 256 Gbytes
PFx_BAR0_APERTURE_SIZE_20x000000047432rwNormal read/write0x00000000BAR0 Aperture: Specifies the aperture of BAR 0.
[The 32-bit BAR 0 or 64-bit BAR 0-1.]
For Endpoint Mode the encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
For Root Port Mode (PF0 only), the encodings are:
000000 = 4 bytes
000001 = 8 bytes
000010 = 16 bytes
000011 = 32 bytes
000100 = 84 bytes
000101 = 128 bytes
000110 = 256 bytes
000111 = 512 bytes
001000 = 1 Kbytes
001001 = 2 Kbytes
001010 = 4 Kbytes
001011 = 8 Kbytes
001100 = 16 Kbytes
001101 = 32 Kbytes
001110 = 64 Kbytes
001111 = 128 Kbytes
010000 = 256 Kbytes
010001 = 512 Kbytes
010010 = 1 Mbytes
010011 = 2 Mbytes
010100 = 4 Mbytes
010101 = 8 Mbytes
010110 = 16 Mbytes
010111 = 32 Mbytes
011000 = 64 Mbytes
011001 = 128 Mbytes
011010 = 256 Mbytes
011011 = 512 Mbytes
011100 = 1 Gbytes
011101 = 2 Gbytes
011110 = 4 Gbytes
011111 = 8 Gbytes
100000 = 16 Gbytes
100001 = 32 Gbytes
100010 = 64 Gbytes
100011 = 128 Gbytes
100100 = 256 Gbytes
PFx_BAR0_APERTURE_SIZE_30x000000047832rwNormal read/write0x00000000BAR0 Aperture: Specifies the aperture of BAR 0.
[The 32-bit BAR 0 or 64-bit BAR 0-1.]
For Endpoint Mode the encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
For Root Port Mode (PF0 only), the encodings are:
000000 = 4 bytes
000001 = 8 bytes
000010 = 16 bytes
000011 = 32 bytes
000100 = 84 bytes
000101 = 128 bytes
000110 = 256 bytes
000111 = 512 bytes
001000 = 1 Kbytes
001001 = 2 Kbytes
001010 = 4 Kbytes
001011 = 8 Kbytes
001100 = 16 Kbytes
001101 = 32 Kbytes
001110 = 64 Kbytes
001111 = 128 Kbytes
010000 = 256 Kbytes
010001 = 512 Kbytes
010010 = 1 Mbytes
010011 = 2 Mbytes
010100 = 4 Mbytes
010101 = 8 Mbytes
010110 = 16 Mbytes
010111 = 32 Mbytes
011000 = 64 Mbytes
011001 = 128 Mbytes
011010 = 256 Mbytes
011011 = 512 Mbytes
011100 = 1 Gbytes
011101 = 2 Gbytes
011110 = 4 Gbytes
011111 = 8 Gbytes
100000 = 16 Gbytes
100001 = 32 Gbytes
100010 = 64 Gbytes
100011 = 128 Gbytes
100100 = 256 Gbytes
PFx_BAR1_CONTROL_00x000000047C32rwNormal read/write0x00000000BAR1 Control - Specifies the configuration of BAR 1.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_BAR1_CONTROL_10x000000048032rwNormal read/write0x00000000BAR1 Control - Specifies the configuration of BAR 1.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_BAR1_CONTROL_20x000000048432rwNormal read/write0x00000000BAR1 Control - Specifies the configuration of BAR 1.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_BAR1_CONTROL_30x000000048832rwNormal read/write0x00000000BAR1 Control - Specifies the configuration of BAR 1.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_BAR1_APERTURE_SIZE_00x000000048C32rwNormal read/write0x00000000BAR1 Aperture: Specifies the aperture of
BAR 1.
For Endpoint Mode the valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
For Root Port Mode (PF0 only), the valid encodings are:
00000 = 4 bytes
00001 = 8 bytes
00010 = 16 bytes
00011 = 32 bytes
00100 = 84 bytes
00101 = 128 bytes
00110 = 256 bytes
00111 = 512 bytes
01000 = 1 Kbytes
01001 = 2 Kbytes
01010 = 4 Kbytes
01011 = 8 Kbytes
01100 = 16 Kbytes
01101 = 32 Kbytes
01110 = 64 Kbytes
01111 = 128 Kbytes
10000 = 256 Kbytes
10001 = 512 Kbytes
10010 = 1 Mbytes
10011 = 2 Mbytes
10100 = 4 Mbytes
10101 = 8 Mbytes
10110 = 16 Mbytes
10111 = 32 Mbytes
11000 = 64 Mbytes
11001 = 128 Mbytes
11010 = 256 Mbytes
11011 = 512 Mbytes
11100 = 1 Gbytes
11101 = 2 Gbytes
PFx_BAR1_APERTURE_SIZE_10x000000049032rwNormal read/write0x00000000BAR1 Aperture: Specifies the aperture of
BAR 1.
For Endpoint Mode the valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
For Root Port Mode (PF0 only), the valid encodings are:
00000 = 4 bytes
00001 = 8 bytes
00010 = 16 bytes
00011 = 32 bytes
00100 = 84 bytes
00101 = 128 bytes
00110 = 256 bytes
00111 = 512 bytes
01000 = 1 Kbytes
01001 = 2 Kbytes
01010 = 4 Kbytes
01011 = 8 Kbytes
01100 = 16 Kbytes
01101 = 32 Kbytes
01110 = 64 Kbytes
01111 = 128 Kbytes
10000 = 256 Kbytes
10001 = 512 Kbytes
10010 = 1 Mbytes
10011 = 2 Mbytes
10100 = 4 Mbytes
10101 = 8 Mbytes
10110 = 16 Mbytes
10111 = 32 Mbytes
11000 = 64 Mbytes
11001 = 128 Mbytes
11010 = 256 Mbytes
11011 = 512 Mbytes
11100 = 1 Gbytes
11101 = 2 Gbytes
PFx_BAR1_APERTURE_SIZE_20x000000049432rwNormal read/write0x00000000BAR1 Aperture: Specifies the aperture of
BAR 1.
For Endpoint Mode the valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
For Root Port Mode (PF0 only), the valid encodings are:
00000 = 4 bytes
00001 = 8 bytes
00010 = 16 bytes
00011 = 32 bytes
00100 = 84 bytes
00101 = 128 bytes
00110 = 256 bytes
00111 = 512 bytes
01000 = 1 Kbytes
01001 = 2 Kbytes
01010 = 4 Kbytes
01011 = 8 Kbytes
01100 = 16 Kbytes
01101 = 32 Kbytes
01110 = 64 Kbytes
01111 = 128 Kbytes
10000 = 256 Kbytes
10001 = 512 Kbytes
10010 = 1 Mbytes
10011 = 2 Mbytes
10100 = 4 Mbytes
10101 = 8 Mbytes
10110 = 16 Mbytes
10111 = 32 Mbytes
11000 = 64 Mbytes
11001 = 128 Mbytes
11010 = 256 Mbytes
11011 = 512 Mbytes
11100 = 1 Gbytes
11101 = 2 Gbytes
PFx_BAR1_APERTURE_SIZE_30x000000049832rwNormal read/write0x00000000BAR1 Aperture: Specifies the aperture of
BAR 1.
For Endpoint Mode the valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
For Root Port Mode (PF0 only), the valid encodings are:
00000 = 4 bytes
00001 = 8 bytes
00010 = 16 bytes
00011 = 32 bytes
00100 = 84 bytes
00101 = 128 bytes
00110 = 256 bytes
00111 = 512 bytes
01000 = 1 Kbytes
01001 = 2 Kbytes
01010 = 4 Kbytes
01011 = 8 Kbytes
01100 = 16 Kbytes
01101 = 32 Kbytes
01110 = 64 Kbytes
01111 = 128 Kbytes
10000 = 256 Kbytes
10001 = 512 Kbytes
10010 = 1 Mbytes
10011 = 2 Mbytes
10100 = 4 Mbytes
10101 = 8 Mbytes
10110 = 16 Mbytes
10111 = 32 Mbytes
11000 = 64 Mbytes
11001 = 128 Mbytes
11010 = 256 Mbytes
11011 = 512 Mbytes
11100 = 1 Gbytes
11101 = 2 Gbytes
PFx_BAR2_CONTROL_00x000000049C32rwNormal read/write0x00000000BAR2 Control - Specifies the configuration of BAR 2.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
2-3, non-prefetchable
111: Part of 64-bit memory BAR
2-3, prefetchable
PFx_BAR2_CONTROL_10x00000004A032rwNormal read/write0x00000000BAR2 Control - Specifies the configuration of BAR 2.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
2-3, non-prefetchable
111: Part of 64-bit memory BAR
2-3, prefetchable
PFx_BAR2_CONTROL_20x00000004A432rwNormal read/write0x00000000BAR2 Control - Specifies the configuration of BAR 2.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
2-3, non-prefetchable
111: Part of 64-bit memory BAR
2-3, prefetchable
PFx_BAR2_CONTROL_30x00000004A832rwNormal read/write0x00000000BAR2 Control - Specifies the configuration of BAR 2.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
2-3, non-prefetchable
111: Part of 64-bit memory BAR
2-3, prefetchable
PFx_BAR2_APERTURE_SIZE_00x00000004AC32rwNormal read/write0x00000000BAR2 Aperture: Specifies the aperture of BAR 2.
[The 32-bit BAR 2 or 64-bit BAR2-3.]
The encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_BAR2_APERTURE_SIZE_10x00000004B032rwNormal read/write0x00000000BAR2 Aperture: Specifies the aperture of BAR 2.
[The 32-bit BAR 2 or 64-bit BAR2-3.]
The encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_BAR2_APERTURE_SIZE_20x00000004B432rwNormal read/write0x00000000BAR2 Aperture: Specifies the aperture of BAR 2.
[The 32-bit BAR 2 or 64-bit BAR2-3.]
The encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_BAR2_APERTURE_SIZE_30x00000004B832rwNormal read/write0x00000000BAR2 Aperture: Specifies the aperture of BAR 2.
[The 32-bit BAR 2 or 64-bit BAR2-3.]
The encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_BAR3_CONTROL_00x00000004BC32rwNormal read/write0x00000000BAR3 Control - Specifies the configuration of BAR 3.
For Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
For non-Endpoint (Type 1) Config Space, the I/O Base & Limit encodings are:
000: Disabled
001: 16-bit I/O Enabled
011: 32-bit I/O Enabled
010,100-111: Reserved
PFx_BAR3_CONTROL_10x00000004C032rwNormal read/write0x00000000BAR3 Control - Specifies the configuration of BAR 3.
For Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
For non-Endpoint (Type 1) Config Space, the I/O Base & Limit encodings are:
000: Disabled
001: 16-bit I/O Enabled
011: 32-bit I/O Enabled
010,100-111: Reserved
PFx_BAR3_CONTROL_20x00000004C432rwNormal read/write0x00000000BAR3 Control - Specifies the configuration of BAR 3.
For Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
For non-Endpoint (Type 1) Config Space, the I/O Base & Limit encodings are:
000: Disabled
001: 16-bit I/O Enabled
011: 32-bit I/O Enabled
010,100-111: Reserved
PFx_BAR3_CONTROL_30x00000004C832rwNormal read/write0x00000000BAR3 Control - Specifies the configuration of BAR 3.
For Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
For non-Endpoint (Type 1) Config Space, the I/O Base & Limit encodings are:
000: Disabled
001: 16-bit I/O Enabled
011: 32-bit I/O Enabled
010,100-111: Reserved
PFx_BAR3_APERTURE_SIZE_00x00000004CC32rwNormal read/write0x00000000BAR3 Aperture: Specifies the aperture of
BAR 3.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_BAR3_APERTURE_SIZE_10x00000004D032rwNormal read/write0x00000000BAR3 Aperture: Specifies the aperture of
BAR 3.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_BAR3_APERTURE_SIZE_20x00000004D432rwNormal read/write0x00000000BAR3 Aperture: Specifies the aperture of
BAR 3.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_BAR3_APERTURE_SIZE_30x00000004D832rwNormal read/write0x00000000BAR3 Aperture: Specifies the aperture of
BAR 3.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_BAR4_CONTROL_00x00000004DC32rwNormal read/write0x00000000BAR4 Control - Specifies the configuration of BAR 4.
For Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
4-5, non-prefetchable
111: Part of 64-bit memory BAR
4-5, prefetchable
For non-Endpoint (Type 1) Config Space, the Memory Base & Limit encodings are:
000: Disabled (RO)
001: Enabled (RW)
010-111: Reserved
PFx_BAR4_CONTROL_10x00000004E032rwNormal read/write0x00000000BAR4 Control - Specifies the configuration of BAR 4.
For Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
4-5, non-prefetchable
111: Part of 64-bit memory BAR
4-5, prefetchable
For non-Endpoint (Type 1) Config Space, the Memory Base & Limit encodings are:
000: Disabled (RO)
001: Enabled (RW)
010-111: Reserved
PFx_BAR4_CONTROL_20x00000004E432rwNormal read/write0x00000000BAR4 Control - Specifies the configuration of BAR 4.
For Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
4-5, non-prefetchable
111: Part of 64-bit memory BAR
4-5, prefetchable
For non-Endpoint (Type 1) Config Space, the Memory Base & Limit encodings are:
000: Disabled (RO)
001: Enabled (RW)
010-111: Reserved
PFx_BAR4_CONTROL_30x00000004E832rwNormal read/write0x00000000BAR4 Control - Specifies the configuration of BAR 4.
For Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
4-5, non-prefetchable
111: Part of 64-bit memory BAR
4-5, prefetchable
For non-Endpoint (Type 1) Config Space, the Memory Base & Limit encodings are:
000: Disabled (RO)
001: Enabled (RW)
010-111: Reserved
PFx_BAR4_APERTURE_SIZE_00x00000004EC32rwNormal read/write0x00000000BAR4 Aperture: Specifies the aperture of BAR 4.
[The 32-bit BAR 4 or 64-bit BAR4-5.]
The encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_BAR4_APERTURE_SIZE_10x00000004F032rwNormal read/write0x00000000BAR4 Aperture: Specifies the aperture of BAR 4.
[The 32-bit BAR 4 or 64-bit BAR4-5.]
The encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_BAR4_APERTURE_SIZE_20x00000004F432rwNormal read/write0x00000000BAR4 Aperture: Specifies the aperture of BAR 4.
[The 32-bit BAR 4 or 64-bit BAR4-5.]
The encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_BAR4_APERTURE_SIZE_30x00000004F832rwNormal read/write0x00000000BAR4 Aperture: Specifies the aperture of BAR 4.
[The 32-bit BAR 4 or 64-bit BAR4-5.]
The encodings are:
000000 = 128bytes
000001 = 256bytes
000010 = 512bytes
000011 = 1 Kbytes
000100 = 2 Kbytes
000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011 = 1 Pbytes
101100 = 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101 = 1 Ebytes
110110 = 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_BAR5_CONTROL_00x00000004FC32rwNormal read/write0x00000000BAR5 Control - Specifies the configuration of BAR 5.
The Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
For non-Endpoint (Type 1) Config Space, the Prefetchable Memory Base & Limit encodings are:
000: Disabled
001: 32-bit Enabled
011: 64-bit Enabled
010,100-111: Reserved
NOTE: For non-Endpoint (Type 1) Config Space, BAR 5 Aperture must be programmed to 0.
PFx_BAR5_CONTROL_10x000000050032rwNormal read/write0x00000000BAR5 Control - Specifies the configuration of BAR 5.
The Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
For non-Endpoint (Type 1) Config Space, the Prefetchable Memory Base & Limit encodings are:
000: Disabled
001: 32-bit Enabled
011: 64-bit Enabled
010,100-111: Reserved
NOTE: For non-Endpoint (Type 1) Config Space, BAR 5 Aperture must be programmed to 0.
PFx_BAR5_CONTROL_20x000000050432rwNormal read/write0x00000000BAR5 Control - Specifies the configuration of BAR 5.
The Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
For non-Endpoint (Type 1) Config Space, the Prefetchable Memory Base & Limit encodings are:
000: Disabled
001: 32-bit Enabled
011: 64-bit Enabled
010,100-111: Reserved
NOTE: For non-Endpoint (Type 1) Config Space, BAR 5 Aperture must be programmed to 0.
PFx_BAR5_CONTROL_30x000000050832rwNormal read/write0x00000000BAR5 Control - Specifies the configuration of BAR 5.
The Endpoint, the various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
For non-Endpoint (Type 1) Config Space, the Prefetchable Memory Base & Limit encodings are:
000: Disabled
001: 32-bit Enabled
011: 64-bit Enabled
010,100-111: Reserved
NOTE: For non-Endpoint (Type 1) Config Space, BAR 5 Aperture must be programmed to 0.
PFx_BAR5_APERTURE_SIZE_00x000000050C32rwNormal read/write0x00000000BAR5 Aperture: Specifies the aperture of
BAR 5.
For Endpoint, the valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes+M417
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
For non-Endpoint (Type 1) Config Space, BAR 5 Aperture must be programmed to 0.
PFx_BAR5_APERTURE_SIZE_10x000000051032rwNormal read/write0x00000000BAR5 Aperture: Specifies the aperture of
BAR 5.
For Endpoint, the valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes+M417
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
For non-Endpoint (Type 1) Config Space, BAR 5 Aperture must be programmed to 0.
PFx_BAR5_APERTURE_SIZE_20x000000051432rwNormal read/write0x00000000BAR5 Aperture: Specifies the aperture of
BAR 5.
For Endpoint, the valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes+M417
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
For non-Endpoint (Type 1) Config Space, BAR 5 Aperture must be programmed to 0.
PFx_BAR5_APERTURE_SIZE_30x000000051832rwNormal read/write0x00000000BAR5 Aperture: Specifies the aperture of
BAR 5.
For Endpoint, the valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes+M417
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
For non-Endpoint (Type 1) Config Space, BAR 5 Aperture must be programmed to 0.
PFx_EXPANSION_ROM_ENABLE_00x000000051C32rwNormal read/write0x00000000PFx Expansion ROM BAR Enable: This bit must be set to enable the Expansion ROM BAR associated with the Function.
PFx_EXPANSION_ROM_ENABLE_10x000000052032rwNormal read/write0x00000000PFx Expansion ROM BAR Enable: This bit must be set to enable the Expansion ROM BAR associated with the Function.
PFx_EXPANSION_ROM_ENABLE_20x000000052432rwNormal read/write0x00000000PFx Expansion ROM BAR Enable: This bit must be set to enable the Expansion ROM BAR associated with the Function.
PFx_EXPANSION_ROM_ENABLE_30x000000052832rwNormal read/write0x00000000PFx Expansion ROM BAR Enable: This bit must be set to enable the Expansion ROM BAR associated with the Function.
PFx_EXPANSION_ROM_APERTURE_SIZE_00x000000052C32rwNormal read/write0x00000000PFx Expansion ROM BAR Aperture Size:
Encoding is as follows:
00000-00011 = Reserved
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,
01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,
01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 - 11111 = Reserved
PFx_EXPANSION_ROM_APERTURE_SIZE_10x000000053032rwNormal read/write0x00000000PFx Expansion ROM BAR Aperture Size:
Encoding is as follows:
00000-00011 = Reserved
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,
01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,
01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 - 11111 = Reserved
PFx_EXPANSION_ROM_APERTURE_SIZE_20x000000053432rwNormal read/write0x00000000PFx Expansion ROM BAR Aperture Size:
Encoding is as follows:
00000-00011 = Reserved
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,
01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,
01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 - 11111 = Reserved
PFx_EXPANSION_ROM_APERTURE_SIZE_30x000000053832rwNormal read/write0x00000000PFx Expansion ROM BAR Aperture Size:
Encoding is as follows:
00000-00011 = Reserved
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,
01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,
01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 - 11111 = Reserved
zFx_PCIE_CAP_NEXTPTR_00x000000053C32rwNormal read/write0x00000000PCIe
Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_PCIE_CAP_NEXTPTR_10x000000054032rwNormal read/write0x00000000PCIe
Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_PCIE_CAP_NEXTPTR_20x000000054432rwNormal read/write0x00000000PCIe
Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_PCIE_CAP_NEXTPTR_30x000000054832rwNormal read/write0x00000000PCIe
Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_PCIE_CAP_NEXTPTR_40x000000054C32rwNormal read/write0x00000000PCIe
Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_PCIE_CAP_NEXTPTR_50x000000055032rwNormal read/write0x00000000PCIe
Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_PCIE_CAP_NEXTPTR_60x000000055432rwNormal read/write0x00000000PCIe
Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_PCIE_CAP_NEXTPTR_70x000000055832rwNormal read/write0x00000000PCIe
Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
PFx_DEV_CAP_MAX_PAYLOAD_SIZE_00x000000055C32rwNormal read/write0x00000000Capability Max Payload Size. This field indicates the maximum payload size that the Function can support for TLPs.
Defined encodings are:
000b - 128 bytes max payload size
001b - 256 bytes max payload size
010b - 512 bytes max payload size
(Reserved for Soft SRIOV)
011b - 1024 bytes max payload size (Reserved for Soft SRIOV)
PFx_DEV_CAP_MAX_PAYLOAD_SIZE_10x000000056032rwNormal read/write0x00000000Capability Max Payload Size. This field indicates the maximum payload size that the Function can support for TLPs.
Defined encodings are:
000b - 128 bytes max payload size
001b - 256 bytes max payload size
010b - 512 bytes max payload size
(Reserved for Soft SRIOV)
011b - 1024 bytes max payload size (Reserved for Soft SRIOV)
PFx_DEV_CAP_MAX_PAYLOAD_SIZE_20x000000056432rwNormal read/write0x00000000Capability Max Payload Size. This field indicates the maximum payload size that the Function can support for TLPs.
Defined encodings are:
000b - 128 bytes max payload size
001b - 256 bytes max payload size
010b - 512 bytes max payload size
(Reserved for Soft SRIOV)
011b - 1024 bytes max payload size (Reserved for Soft SRIOV)
PFx_DEV_CAP_MAX_PAYLOAD_SIZE_30x000000056832rwNormal read/write0x00000000Capability Max Payload Size. This field indicates the maximum payload size that the Function can support for TLPs.
Defined encodings are:
000b - 128 bytes max payload size
001b - 256 bytes max payload size
010b - 512 bytes max payload size
(Reserved for Soft SRIOV)
011b - 1024 bytes max payload size (Reserved for Soft SRIOV)
PF0_DEV_CAP_EXT_TAG_SUPPORTED0x000000056C32rwNormal read/write0x00000000Extended Tags support. FALSE - 5-bit tag, TRUE - 8-bit tag
PF0_DEV_CAP_ENDPOINT_L0S_LATENCY0x000000057032rwNormal read/write0x00000000Endpoint L0s Acceptable Latency.
Records the latency the endpoint can withstand on transitions from L0s state to L0.
Valid settings are:
0h less than 64ns, 1h 64 to 128ns, 2h 128 to 256ns, 3h 256 to 512ns, 4h 512ns to 1us, 5h 1 to 2us, 6h 2 to 4 us, 7h more than 4us.
For Endpoints only.
Must be 0h for other devices.
PF0_DEV_CAP_ENDPOINT_L1_LATENCY0x000000057432rwNormal read/write0x00000000Endpoint L1 Acceptable Latency.
Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 state supported).
Valid settings are:
0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us.
For Endpoints only.
Must be 0h for other devices.
PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE0x000000057832rwNormal read/write0x00000000Function Level Reset: Set TRUE when device has Function-Level Reset capability.
PF0_LINK_CAP_ASPM_SUPPORT0x000000057C32rwNormal read/write0x00000000Active State PM Support.
Indicates the level of active state power management supported by the selected PCI Express Link, encoded as follows:
00b = No ASPM, 01b = L0s
supported, 10b = L1 supported,
11b = L0s and L1 entry supported. Supported encodings are 00b, 01b and 10b. PF0_LINK_CAP_ASPM_SUPPORT = 11b is not supported. When PL_LINK_CAP_MAX_LINK_SPEED 0100 (Gen3) or 1000 (Gen4), PF0_LINK_CAP_ASPM_SUPPORT must be set to either 00b or 10b.
PF0_LINK_CONTROL_RCB0x000000058032rwNormal read/write0x00000000Read Completion Boundary (RCB). Root Port (PL_UPSTREAM_FACING is FALSE and IS_SWITCH_PORT = FALSE) 0b = 0b 64B RCB or 1b = 128B RCB. Not applicable for all other Port configurations.
PF0_LINK_STATUS_SLOT_CLOCK_CONFIG0x000000058432rwNormal read/write0x00000000Slot Clock Configuration. "TRUE" if devce uses clock provided on slot connector, else "FALSE"
if the device uses an independent clock irrespective of the presence of a reference on the connector.
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN10x000000058832rwNormal read/write0x00000000Sets the exit latency from L0s state to be applied (at 2.5G) where a common clock is used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN20x000000058C32rwNormal read/write0x00000000Sets the exit latency from L0s state to be applied (at 5G) where a common clock is used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN30x000000059032rwNormal read/write0x00000000Sets the exit latency from L0s state to be applied (at 8G) where a common clock is used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN40x000000059432rwNormal read/write0x00000000Sets the exit latency from L0s state to be applied (at 16G) where a common clock is used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN10x000000059832rwNormal read/write0x00000000Sets the exit latency from L0s state to be applied (at 2.5G) where separate clocks are used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN20x000000059C32rwNormal read/write0x00000000Sets the exit latency from L0s state to be applied (at 5G) where separate clocks are used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN30x00000005A032rwNormal read/write0x00000000Sets the exit latency from L0s state to be applied (at 8G) where separate clocks are used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN40x00000005A432rwNormal read/write0x00000000Sets the exit latency from L0s state to be applied (at 16G) where separate clocks are used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN10x00000005A832rwNormal read/write0x00000000Sets the exit latency from L1 state to be applied (at 2.5G) where a common clock is used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN20x00000005AC32rwNormal read/write0x00000000Sets the exit latency from L1 state to be applied (at 5G) where a common clock is used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN30x00000005B032rwNormal read/write0x00000000Sets the exit latency from L1 state to be applied (at 8G) where a common clock is used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN40x00000005B432rwNormal read/write0x00000000Sets the exit latency from L1 state to be applied (at 16G) where a common clock is used.
Transferred to the Link Capabilities register.
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN10x00000005B832rwNormal read/write0x00000000Sets the exit latency from L1 state to be applied (at 2.5G) where separate clocks are used. Transferred to the Link Capabilities register.
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN20x00000005BC32rwNormal read/write0x00000000Sets the exit latency from L1 state to be applied (at 5G) where separate clocks are used. Transferred to the Link Capabilities register.
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN30x00000005C032rwNormal read/write0x00000000Sets the exit latency from L1 state to be applied (at 8G) where separate clocks are used. Transferred to the Link Capabilities register.
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN40x00000005C432rwNormal read/write0x00000000Sets the exit latency from L1 state to be applied (at 16G) where separate clocks are used. Transferred to the Link Capabilities register.
PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE0x00000005C832rwNormal read/write0x00000000Completion Timeout Disable Capable: A TRUE sets Bit 4, indicates that the associated Function supports the capability to turn off its Completion timeout.
PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT0x00000005CC32rwNormal read/write0x0000000032-bit AtomicOp Completer Supported: if TRUE sets Bit 7, includes FetchAdd, Swap, and CAS AtomicOps optional capability.
PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT0x00000005D032rwNormal read/write0x0000000064-bit AtomicOp Completer Supported:
If TRUE sets Bit 8, includes FetchAdd, Swap, and CAS AtomicOps optional capability.
PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT0x00000005D432rwNormal read/write0x00000000128-bit CAS Completer Supported:
If TRUE sets Bit 9, enables optional capability.
PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT0x00000005DC32rwNormal read/write0x00000000TPH Completer Supported:
Sets Bit 12, value indicates Completer support for TPH. Supported Encodings are:
0b = TPH and Extended TPH Completer not supported.
1b = TPH Completer supported.
PF0_DEV_CAP2_OBFF_SUPPORT0x00000005E032rwNormal read/write0x00000000OBFF Supported: Sets Bits 19:18,
00b - OBFF Not Supported
01b - 11b - Reserved (OBFF functionality not supported)
PF0_DEV_CAP2_ARI_FORWARD_ENABLE0x00000005E432rwNormal read/write0x00000000ARI Forwarding Supported: This bit must be set to TRUE if Root Port supports this optional capability.
PF0_DEV_CONTROL2_PERMIT_IDO_REQ_EN0x00000005E832rwNormal read/write0x00000000Permit IDO Requester Enable: Permit IO Req by making Device Control2 IO Reqester Enable bit RW (HW does not support IDO)
PF0_DEV_CONTROL2_PERMIT_IDO_CPL_EN0x00000005EC32rwNormal read/write0x00000000Permit IDO Completer Enable: Permit IO Req by making Device Control2 IO Completer Enable bit RW (HW does not support IDO)
PFx_MSI_CAP_NEXTPTR_00x00000005F032rwNormal read/write0x00000000MSI Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
PFx_MSI_CAP_NEXTPTR_10x00000005F432rwNormal read/write0x00000000MSI Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
PFx_MSI_CAP_NEXTPTR_20x00000005F832rwNormal read/write0x00000000MSI Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
PFx_MSI_CAP_NEXTPTR_30x00000005FC32rwNormal read/write0x00000000MSI Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
PFx_MSI_CAP_PERVECMASKCAP_00x000000060032rwNormal read/write0x00000000MSI Capabilitys Per Vector Masking bit: When set to TRUE to indicate that the device has per-vector masking capability.
PFx_MSI_CAP_PERVECMASKCAP_10x000000060432rwNormal read/write0x00000000MSI Capabilitys Per Vector Masking bit: When set to TRUE to indicate that the device has per-vector masking capability.
PFx_MSI_CAP_PERVECMASKCAP_20x000000060832rwNormal read/write0x00000000MSI Capabilitys Per Vector Masking bit: When set to TRUE to indicate that the device has per-vector masking capability.
PFx_MSI_CAP_PERVECMASKCAP_30x000000060C32rwNormal read/write0x00000000MSI Capabilitys Per Vector Masking bit: When set to TRUE to indicate that the device has per-vector masking capability.
PFx_MSI_CAP_MULTIMSGCAP_00x000000061032rwNormal read/write0x00000000Multiple Message Capable Sets Bits [19:17] in the Control register. Each MSI function may request up to 32 unique messages.
System software may read this field to determine the number of messages requested.
Number of messages requested are encoded as follows:
0h= 1 vector
1h=
2 vectors
2h=
4.vectors
3h=
8 vectors
4h= 16 vectors
5h= 32 vectors
6h, 7h =
Rsvd
PFx_MSI_CAP_MULTIMSGCAP_10x000000061432rwNormal read/write0x00000000Multiple Message Capable Sets Bits [19:17] in the Control register. Each MSI function may request up to 32 unique messages.
System software may read this field to determine the number of messages requested.
Number of messages requested are encoded as follows:
0h= 1 vector
1h=
2 vectors
2h=
4.vectors
3h=
8 vectors
4h= 16 vectors
5h= 32 vectors
6h, 7h =
Rsvd
PFx_MSI_CAP_MULTIMSGCAP_20x000000061832rwNormal read/write0x00000000Multiple Message Capable Sets Bits [19:17] in the Control register. Each MSI function may request up to 32 unique messages.
System software may read this field to determine the number of messages requested.
Number of messages requested are encoded as follows:
0h= 1 vector
1h=
2 vectors
2h=
4.vectors
3h=
8 vectors
4h= 16 vectors
5h= 32 vectors
6h, 7h =
Rsvd
PFx_MSI_CAP_MULTIMSGCAP_30x000000061C32rwNormal read/write0x00000000Multiple Message Capable Sets Bits [19:17] in the Control register. Each MSI function may request up to 32 unique messages.
System software may read this field to determine the number of messages requested.
Number of messages requested are encoded as follows:
0h= 1 vector
1h=
2 vectors
2h=
4.vectors
3h=
8 vectors
4h= 16 vectors
5h= 32 vectors
6h, 7h =
Rsvd
zFx_MSIX_CAP_NEXTPTR_00x000000062032rwNormal read/write0x00000000MSI-X Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_MSIX_CAP_NEXTPTR_10x000000062432rwNormal read/write0x00000000MSI-X Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_MSIX_CAP_NEXTPTR_20x000000062832rwNormal read/write0x00000000MSI-X Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_MSIX_CAP_NEXTPTR_30x000000062C32rwNormal read/write0x00000000MSI-X Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_MSIX_CAP_NEXTPTR_40x000000063032rwNormal read/write0x00000000MSI-X Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_MSIX_CAP_NEXTPTR_50x000000063432rwNormal read/write0x00000000MSI-X Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_MSIX_CAP_NEXTPTR_60x000000063832rwNormal read/write0x00000000MSI-X Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_MSIX_CAP_NEXTPTR_70x000000063C32rwNormal read/write0x00000000MSI-X Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.
zFx_MSIX_CAP_PBA_BIR_00x000000064032rwNormal read/write0x00000000MSI-X Pending Bit Array BIR. This value is transferred to the MSI-X PBA BIR field. Set to 0 if MSI-X is not enabled. When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_BIR_10x000000064432rwNormal read/write0x00000000MSI-X Pending Bit Array BIR. This value is transferred to the MSI-X PBA BIR field. Set to 0 if MSI-X is not enabled. When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_BIR_20x000000064832rwNormal read/write0x00000000MSI-X Pending Bit Array BIR. This value is transferred to the MSI-X PBA BIR field. Set to 0 if MSI-X is not enabled. When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_BIR_30x000000064C32rwNormal read/write0x00000000MSI-X Pending Bit Array BIR. This value is transferred to the MSI-X PBA BIR field. Set to 0 if MSI-X is not enabled. When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_BIR_40x000000065032rwNormal read/write0x00000000MSI-X Pending Bit Array BIR. This value is transferred to the MSI-X PBA BIR field. Set to 0 if MSI-X is not enabled. When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_BIR_50x000000065432rwNormal read/write0x00000000MSI-X Pending Bit Array BIR. This value is transferred to the MSI-X PBA BIR field. Set to 0 if MSI-X is not enabled. When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_BIR_60x000000065832rwNormal read/write0x00000000MSI-X Pending Bit Array BIR. This value is transferred to the MSI-X PBA BIR field. Set to 0 if MSI-X is not enabled. When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_BIR_70x000000065C32rwNormal read/write0x00000000MSI-X Pending Bit Array BIR. This value is transferred to the MSI-X PBA BIR field. Set to 0 if MSI-X is not enabled. When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_OFFSET_00x000000066032rwNormal read/write0x00000000MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_OFFSET_10x000000066432rwNormal read/write0x00000000MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_OFFSET_20x000000066832rwNormal read/write0x00000000MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_OFFSET_30x000000066C32rwNormal read/write0x00000000MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_OFFSET_40x000000067032rwNormal read/write0x00000000MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_OFFSET_50x000000067432rwNormal read/write0x00000000MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_OFFSET_60x000000067832rwNormal read/write0x00000000MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_PBA_OFFSET_70x000000067C32rwNormal read/write0x00000000MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_BIR_00x000000068032rwNormal read/write0x00000000MSI-X Table BIR. This value is transferred to the MSI-X Table BIR field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_BIR_10x000000068432rwNormal read/write0x00000000MSI-X Table BIR. This value is transferred to the MSI-X Table BIR field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_BIR_20x000000068832rwNormal read/write0x00000000MSI-X Table BIR. This value is transferred to the MSI-X Table BIR field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_BIR_30x000000068C32rwNormal read/write0x00000000MSI-X Table BIR. This value is transferred to the MSI-X Table BIR field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_BIR_40x000000069032rwNormal read/write0x00000000MSI-X Table BIR. This value is transferred to the MSI-X Table BIR field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_BIR_50x000000069432rwNormal read/write0x00000000MSI-X Table BIR. This value is transferred to the MSI-X Table BIR field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_BIR_60x000000069832rwNormal read/write0x00000000MSI-X Table BIR. This value is transferred to the MSI-X Table BIR field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_BIR_70x000000069C32rwNormal read/write0x00000000MSI-X Table BIR. This value is transferred to the MSI-X Table BIR field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_OFFSET_00x00000006A032rwNormal read/write0x00000000MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_OFFSET_10x00000006A432rwNormal read/write0x00000000MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_OFFSET_20x00000006A832rwNormal read/write0x00000000MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_OFFSET_30x00000006AC32rwNormal read/write0x00000000MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_OFFSET_40x00000006B032rwNormal read/write0x00000000MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_OFFSET_50x00000006B432rwNormal read/write0x00000000MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_OFFSET_60x00000006B832rwNormal read/write0x00000000MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_OFFSET_70x00000006BC32rwNormal read/write0x00000000MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.When AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = TRUE, only PF0 value will be used.
zFx_MSIX_CAP_TABLE_SIZE_00x00000006C032rwNormal read/write0x00000000MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic.
zFx_MSIX_CAP_TABLE_SIZE_10x00000006C432rwNormal read/write0x00000000MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic.
zFx_MSIX_CAP_TABLE_SIZE_20x00000006C832rwNormal read/write0x00000000MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic.
zFx_MSIX_CAP_TABLE_SIZE_30x00000006CC32rwNormal read/write0x00000000MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic.
zFx_MSIX_CAP_TABLE_SIZE_40x00000006D032rwNormal read/write0x00000000MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic.
zFx_MSIX_CAP_TABLE_SIZE_50x00000006D432rwNormal read/write0x00000000MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic.
zFx_MSIX_CAP_TABLE_SIZE_60x00000006D832rwNormal read/write0x00000000MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic.
zFx_MSIX_CAP_TABLE_SIZE_70x00000006DC32rwNormal read/write0x00000000MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic.
PF0_PM_CAP_ID0x00000006E432rwNormal read/write0x00000000PM Capability ID: Identifies that the capability structure is for Power Management. Applies to all PFs
PFx_PM_CAP_NEXTPTR_00x00000006E832rwNormal read/write0x00000000PM Capability Next Cap Pointer: Contains pointer to the next PCI Capability Structure.
PFx_PM_CAP_NEXTPTR_10x00000006EC32rwNormal read/write0x00000000PM Capability Next Cap Pointer: Contains pointer to the next PCI Capability Structure.
PFx_PM_CAP_NEXTPTR_20x00000006F032rwNormal read/write0x00000000PM Capability Next Cap Pointer: Contains pointer to the next PCI Capability Structure.
PFx_PM_CAP_NEXTPTR_30x00000006F432rwNormal read/write0x00000000PM Capability Next Cap Pointer: Contains pointer to the next PCI Capability Structure.
PF0_PM_CAP_PMESUPPORT_D3HOT0x00000006F832rwNormal read/write0x00000000PME Support for D3hot State: Sets Bit 14 of PMC Register when TRUE. All functions assume value programmed into PF0.
PF0_PM_CAP_PMESUPPORT_D3COLD0x00000006FC32rwNormal read/write0x00000000PME Support for D3hot State: Sets Bit 14 of PMC Register when TRUE. All functions assume value programmed into PF0.
PF0_PM_CAP_PMESUPPORT_D10x000000070032rwNormal read/write0x00000000PME Support for D1 State: Sets Bit 12 of PMC Register when TRUE. All functions assume value programmed into PF0.
PF0_PM_CAP_PMESUPPORT_D00x000000070432rwNormal read/write0x00000000PME Support for D0 State: Sets Bit 11 of PMC Register when TRUE. All functions assume value programmed into PF0.
PF0_PM_CAP_SUPP_D1_STATE0x000000070832rwNormal read/write0x00000000D1_Support for D0 State: Sets Bit 9 of PMC Register when TRUE. All functions assume value programmed into PF0.
PF0_PM_CAP_VER_ID0x000000070C32rwNormal read/write0x00000000Version of PM Spacification: Indicates the version of the PCI Bus Power Management Specifications that the Function implements. Applies to all PFs
PF0_PM_CSR_NOSOFTRESET0x000000071032rwNormal read/write0x00000000No_Soft_Reset: Power Management CSR [3] "No Soft Reset" bit. All functions assume value programmed into PF0.
PM_ENABLE_L23_ENTRY0x000000071432rwNormal read/write0x00000000Root Port Enter L23 Enable: When set to FALSE, Block will not transition the Physical link state to L2/L3 when its link partner enters the L23_Ready power management state. When (optionally) set to TRUE, the Blockwill transition Physical link state to L2/L3 Idle when the link partner enters L23_Ready. Once the Block enters L2/L3 Idle, a reset is needed to transition it out of L2/L3 Idle.
DNSTREAM_LINK_NUM0x000000071832rwNormal read/write0x00000000Used in downstream facing mode only. Specified the link number that this device will advertise in TS1 and TS2 during link training.
ROOT_CAP_CRS_SW_VISIBILITY0x000000071C32rwNormal read/write0x00000000When TRUE, sets the Root Capability CRS Software Visibility bit to indicate that the Root port is capable of returning received Configuration Request Retry Status (CRS) Completion Status to software.
When FALSE, the Root Capability CRS Software Visibility bit is set to 0.
AER_CAP_PERMIT_ROOTERR_UPDATE0x000000072032rwNormal read/write0x00000000When TRUE, enables updates for Root AER registers Root Error Status and Error Source ID.
When FALSE, disables updates to the Root AER registers Root Error Status and Error Source ID.
When FALSE, disables these register updates.
LINK_CONTROL2_SELECTABLE_DEEMPH0x000000072432rwNormal read/write0x00000000Link Control2 Selectable Deemph:
Allows configurablity of Link Control2 Selectable Deemph
AUTO_FLR_RESPONSE0x000000072832rwNormal read/write0x00000000When FALSE: cfg_flr_done behavior is that a 0 -> 1 edge and valid function number on the input is used to signal that flr is complete for that function. When TRUE:
cfg_flr_done inputs are tied to 1, so there is no user response required.
DELAYED_FLR0x000000072C32rwNormal read/write0x00000000When FALSE: Original FLR behavior.
When TRUE: New FLR behavior. Resetting of registers in the target function is delayed until after user response (cfg_flr_done, cfg_vf_flr_done) is r received.
PFx_DSN_CAP_NEXTPTR_00x000000073032rwNormal read/write0x00000000Device Serial Number Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.
PFx_DSN_CAP_NEXTPTR_10x000000073432rwNormal read/write0x00000000Device Serial Number Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.
PFx_DSN_CAP_NEXTPTR_20x000000073832rwNormal read/write0x00000000Device Serial Number Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.
PFx_DSN_CAP_NEXTPTR_30x000000073C32rwNormal read/write0x00000000Device Serial Number Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.
DSN_CAP_ENABLE0x000000074032rwNormal read/write0x00000000DSN Structure Enable
When TRUE, enables DSN. When FALSE, hides the capability completely
PF0_VC_CAP_VER0x000000074432rwNormal read/write0x00000000VC Capability Version
PF0_VC_CAP_NEXTPTR0x000000074832rwNormal read/write0x00000000VC Next Capability Pointer
PF0_VC_CAP_ENABLE0x000000074C32rwNormal read/write0x00000000VC Capability Structure Enable
When TRUE, enabled VC0-TCx operation. When FALSE, hides the capability completely (VC0-TC0 operation).
PF0_VC_ARB_TBL_OFFSET0x000000075032rwNormal read/write0x00000000VC Arbitration Table Offset
PF0_VC_ARB_CAPABILITY0x000000075432rwNormal read/write0x00000000VC Arbitration Capability
PF0_VC_EXTENDED_COUNT0x000000075832rwNormal read/write0x00000000VC Extended Count
PF0_VC_LOW_PRIORITY_EXTENDED_COUNT0x000000075C32rwNormal read/write0x00000000VC Low Priority Extended Count
VC1_BASE_DISABLE0x000000076032rwNormal read/write0x00000000VC Cap Address Change for CCIX: Then FALSE
VC Cap
is at 1F0h, When TRUE VC Cap is at 200h
PF0_SECONDARY_PCIE_CAP_NEXTPTR0x000000076432rwNormal read/write0x00000000Secondary PCIe Next Capability Pointer
PFx_AER_CAP_NEXTPTR_00x000000076832rwNormal read/write0x00000000AERs Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.
PFx_AER_CAP_NEXTPTR_10x000000076C32rwNormal read/write0x00000000AERs Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.
PFx_AER_CAP_NEXTPTR_20x000000077032rwNormal read/write0x00000000AERs Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.
PFx_AER_CAP_NEXTPTR_30x000000077432rwNormal read/write0x00000000AERs Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.
PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE0x000000077832rwNormal read/write0x00000000ECRC Generation and Check capable. Value transferred to bits 7 and 9 of the AER Capabilities and Control Register.
ARI_CAP_ENABLE0x000000077C32rwNormal read/write0x00000000Enable ARI Capability: when FALSE: Enables legacy interpretation of PCI RID {8b Bus#, 5b device#, 3b Function#}; when TRUE: alternate interpretation of PCI RID {8b Bus#, 8b Function#}.
zFx_ARI_CAP_NEXTPTR_00x000000078032rwNormal read/write0x00000000ARI Next Capability Offset: Bits 31:20 ARI Extended Capability Header Register.
zFx_ARI_CAP_NEXTPTR_10x000000078432rwNormal read/write0x00000000ARI Next Capability Offset: Bits 31:20 ARI Extended Capability Header Register.
zFx_ARI_CAP_NEXTPTR_20x000000078832rwNormal read/write0x00000000ARI Next Capability Offset: Bits 31:20 ARI Extended Capability Header Register.
zFx_ARI_CAP_NEXTPTR_30x000000078C32rwNormal read/write0x00000000ARI Next Capability Offset: Bits 31:20 ARI Extended Capability Header Register.
zFx_ARI_CAP_NEXTPTR_40x000000079032rwNormal read/write0x00000000ARI Next Capability Offset: Bits 31:20 ARI Extended Capability Header Register.
zFx_ARI_CAP_NEXTPTR_50x000000079432rwNormal read/write0x00000000ARI Next Capability Offset: Bits 31:20 ARI Extended Capability Header Register.
zFx_ARI_CAP_NEXTPTR_60x000000079832rwNormal read/write0x00000000ARI Next Capability Offset: Bits 31:20 ARI Extended Capability Header Register.
zFx_ARI_CAP_NEXTPTR_70x000000079C32rwNormal read/write0x00000000ARI Next Capability Offset: Bits 31:20 ARI Extended Capability Header Register.
PF0_ARI_CAP_VER0x00000007A032rwNormal read/write0x00000000ARI Capability Version: Bits 19:16 ARI Extended Capability Header Register
PFx_ARI_CAP_NEXT_FUNC_00x00000007A432rwNormal read/write0x00000000ARI Next Function: Bits 15:8 ARI Capability and Control Registers. Points to the next Physical Function in the device.
PFx_ARI_CAP_NEXT_FUNC_10x00000007A832rwNormal read/write0x00000000ARI Next Function: Bits 15:8 ARI Capability and Control Registers. Points to the next Physical Function in the device.
PFx_ARI_CAP_NEXT_FUNC_20x00000007AC32rwNormal read/write0x00000000ARI Next Function: Bits 15:8 ARI Capability and Control Registers. Points to the next Physical Function in the device.
PFx_ARI_CAP_NEXT_FUNC_30x00000007B032rwNormal read/write0x00000000ARI Next Function: Bits 15:8 ARI Capability and Control Registers. Points to the next Physical Function in the device.
SRIOV_CAP_ENABLE0x00000007D032rwNormal read/write0x00000000Enable SRIOV Capability: Single Root I/O Virtualization (SR-IOV) feature is enabled per Phyiscal Function. bit 0 - PF0, bit 1 - PF1 and so on.
ARI_CAP_ENABLE must be enabled when SRIOV_CAP_ENABLE != 0h and the total number of Physical Functions and Virtual Functions supported is > 8
PFx_SRIOV_CAP_NEXTPTR_00x00000007D432rwNormal read/write0x00000000SRIOV Next Capability Offset: Bits 31:20 SRIOV Extended Capability Header Register
PFx_SRIOV_CAP_NEXTPTR_10x00000007D832rwNormal read/write0x00000000SRIOV Next Capability Offset: Bits 31:20 SRIOV Extended Capability Header Register
PFx_SRIOV_CAP_NEXTPTR_20x00000007DC32rwNormal read/write0x00000000SRIOV Next Capability Offset: Bits 31:20 SRIOV Extended Capability Header Register
PFx_SRIOV_CAP_NEXTPTR_30x00000007E032rwNormal read/write0x00000000SRIOV Next Capability Offset: Bits 31:20 SRIOV Extended Capability Header Register
PFx_SRIOV_CAP_VER_00x00000007E432rwNormal read/write0x00000000SRIOV Capability Version: Bits 19:16 SRIOV Extended Capability Header Register
PFx_SRIOV_CAP_VER_10x00000007E832rwNormal read/write0x00000000SRIOV Capability Version: Bits 19:16 SRIOV Extended Capability Header Register
PFx_SRIOV_CAP_VER_20x00000007EC32rwNormal read/write0x00000000SRIOV Capability Version: Bits 19:16 SRIOV Extended Capability Header Register
PFx_SRIOV_CAP_VER_30x00000007F032rwNormal read/write0x00000000SRIOV Capability Version: Bits 19:16 SRIOV Extended Capability Header Register
PFx_SRIOV_ARI_CAPBL_HIER_PRESERVED_00x00000007F432rwNormal read/write0x00000000ARI Capable Hierarchy Preserved: If set to TRUE, the ARI Capable Hierarchy bit is preserved across certain power state transitions.
PFx_SRIOV_ARI_CAPBL_HIER_PRESERVED_10x00000007F832rwNormal read/write0x00000000ARI Capable Hierarchy Preserved: If set to TRUE, the ARI Capable Hierarchy bit is preserved across certain power state transitions.
PFx_SRIOV_ARI_CAPBL_HIER_PRESERVED_20x00000007FC32rwNormal read/write0x00000000ARI Capable Hierarchy Preserved: If set to TRUE, the ARI Capable Hierarchy bit is preserved across certain power state transitions.
PFx_SRIOV_ARI_CAPBL_HIER_PRESERVED_30x000000080032rwNormal read/write0x00000000ARI Capable Hierarchy Preserved: If set to TRUE, the ARI Capable Hierarchy bit is preserved across certain power state transitions.
PFx_SRIOV_CAP_INITIAL_VF_00x000000080432rwNormal read/write0x00000000Initial Number of VFs: Initial number of VFs configured for PF0.
PFx_SRIOV_CAP_INITIAL_VF_10x000000080832rwNormal read/write0x00000000Initial Number of VFs: Initial number of VFs configured for PF0.
PFx_SRIOV_CAP_INITIAL_VF_20x000000080C32rwNormal read/write0x00000000Initial Number of VFs: Initial number of VFs configured for PF0.
PFx_SRIOV_CAP_INITIAL_VF_30x000000081032rwNormal read/write0x00000000Initial Number of VFs: Initial number of VFs configured for PF0.
PFx_SRIOV_CAP_TOTAL_VF_00x000000081432rwNormal read/write0x00000000Total Number of VFs: Total number of VFs configured for PF0. Must be equal to PF0_SRIOV_CAP_INITIAL_VF.
PFx_SRIOV_CAP_TOTAL_VF_10x000000081832rwNormal read/write0x00000000Total Number of VFs: Total number of VFs configured for PF0. Must be equal to PF0_SRIOV_CAP_INITIAL_VF.
PFx_SRIOV_CAP_TOTAL_VF_20x000000081C32rwNormal read/write0x00000000Total Number of VFs: Total number of VFs configured for PF0. Must be equal to PF0_SRIOV_CAP_INITIAL_VF.
PFx_SRIOV_CAP_TOTAL_VF_30x000000082032rwNormal read/write0x00000000Total Number of VFs: Total number of VFs configured for PF0. Must be equal to PF0_SRIOV_CAP_INITIAL_VF.
PFx_SRIOV_FUNC_DEP_LINK_00x000000082432rwNormal read/write0x00000000Physical Function Dependency Link: This field is used to specify dependencies between PFs. The programming model for a Device may have vendor specific dependencies between sets of Functions. The Function Dependency Link field is used to describe these dependencies. Upper 8 bits are reserved/unused.
PFx_SRIOV_FUNC_DEP_LINK_10x000000082832rwNormal read/write0x00000000Physical Function Dependency Link: This field is used to specify dependencies between PFs. The programming model for a Device may have vendor specific dependencies between sets of Functions. The Function Dependency Link field is used to describe these dependencies. Upper 8 bits are reserved/unused.
PFx_SRIOV_FUNC_DEP_LINK_20x000000082C32rwNormal read/write0x00000000Physical Function Dependency Link: This field is used to specify dependencies between PFs. The programming model for a Device may have vendor specific dependencies between sets of Functions. The Function Dependency Link field is used to describe these dependencies. Upper 8 bits are reserved/unused.
PFx_SRIOV_FUNC_DEP_LINK_30x000000083032rwNormal read/write0x00000000Physical Function Dependency Link: This field is used to specify dependencies between PFs. The programming model for a Device may have vendor specific dependencies between sets of Functions. The Function Dependency Link field is used to describe these dependencies. Upper 8 bits are reserved/unused.
PFx_SRIOV_FIRST_VF_OFFSET_00x000000083432rwNormal read/write0x00000000Offset of First VF: Allowed values for the first SR-IOV PF are:
1D (non ARI SR_IOV only), 4D and 64D. For all subsequent SR-IOV enabled PFs value allowed is sum (PFx_SRIOV_CAP_TOTAL_VF + PFx_SRIOV_FIRST_VF_OFFSET -1) taken for the preious SR-IOV PF. 0h if the PF does not support SR-IOV.
PFx_SRIOV_FIRST_VF_OFFSET_10x000000083832rwNormal read/write0x00000000Offset of First VF: Allowed values for the first SR-IOV PF are:
1D (non ARI SR_IOV only), 4D and 64D. For all subsequent SR-IOV enabled PFs value allowed is sum (PFx_SRIOV_CAP_TOTAL_VF + PFx_SRIOV_FIRST_VF_OFFSET -1) taken for the preious SR-IOV PF. 0h if the PF does not support SR-IOV.
PFx_SRIOV_FIRST_VF_OFFSET_20x000000083C32rwNormal read/write0x00000000Offset of First VF: Allowed values for the first SR-IOV PF are:
1D (non ARI SR_IOV only), 4D and 64D. For all subsequent SR-IOV enabled PFs value allowed is sum (PFx_SRIOV_CAP_TOTAL_VF + PFx_SRIOV_FIRST_VF_OFFSET -1) taken for the preious SR-IOV PF. 0h if the PF does not support SR-IOV.
PFx_SRIOV_FIRST_VF_OFFSET_30x000000084032rwNormal read/write0x00000000Offset of First VF: Allowed values for the first SR-IOV PF are:
1D (non ARI SR_IOV only), 4D and 64D. For all subsequent SR-IOV enabled PFs value allowed is sum (PFx_SRIOV_CAP_TOTAL_VF + PFx_SRIOV_FIRST_VF_OFFSET -1) taken for the preious SR-IOV PF. 0h if the PF does not support SR-IOV.
PFx_SRIOV_VF_DEVICE_ID_00x000000084432rwNormal read/write0x00000000VF Device ID assigned to device: This field contains the Device ID that should be presented for every VF
PFx_SRIOV_VF_DEVICE_ID_10x000000084832rwNormal read/write0x00000000VF Device ID assigned to device: This field contains the Device ID that should be presented for every VF
PFx_SRIOV_VF_DEVICE_ID_20x000000084C32rwNormal read/write0x00000000VF Device ID assigned to device: This field contains the Device ID that should be presented for every VF
PFx_SRIOV_VF_DEVICE_ID_30x000000085032rwNormal read/write0x00000000VF Device ID assigned to device: This field contains the Device ID that should be presented for every VF
PFx_SRIOV_SUPPORTED_PAGE_SIZE_00x000000085432rwNormal read/write0x00000000Page Size Supported By Device: This field indicates the page sizes supported by the PF. This PF supports a page size of 2n+12 if bit n is Set
PFx_SRIOV_SUPPORTED_PAGE_SIZE_10x000000085832rwNormal read/write0x00000000Page Size Supported By Device: This field indicates the page sizes supported by the PF. This PF supports a page size of 2n+12 if bit n is Set
PFx_SRIOV_SUPPORTED_PAGE_SIZE_20x000000085C32rwNormal read/write0x00000000Page Size Supported By Device: This field indicates the page sizes supported by the PF. This PF supports a page size of 2n+12 if bit n is Set
PFx_SRIOV_SUPPORTED_PAGE_SIZE_30x000000086032rwNormal read/write0x00000000Page Size Supported By Device: This field indicates the page sizes supported by the PF. This PF supports a page size of 2n+12 if bit n is Set
PFx_SRIOV_BAR0_CONTROL_00x000000086432rwNormal read/write0x00000000VF BAR0 Control - Specifies the configuration of BAR 0.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_SRIOV_BAR0_CONTROL_10x000000086832rwNormal read/write0x00000000VF BAR0 Control - Specifies the configuration of BAR 0.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_SRIOV_BAR0_CONTROL_20x000000086C32rwNormal read/write0x00000000VF BAR0 Control - Specifies the configuration of BAR 0.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_SRIOV_BAR0_CONTROL_30x000000087032rwNormal read/write0x00000000VF BAR0 Control - Specifies the configuration of BAR 0.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_SRIOV_BAR0_APERTURE_SIZE_00x000000087432rwNormal read/write0x00000000VF BAR0 Aperture: Specifies the aperture of the 32-bit BAR 0 or 64-bit BAR 0-1.The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR0_APERTURE_SIZE_10x000000087832rwNormal read/write0x00000000VF BAR0 Aperture: Specifies the aperture of the 32-bit BAR 0 or 64-bit BAR 0-1.The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR0_APERTURE_SIZE_20x000000087C32rwNormal read/write0x00000000VF BAR0 Aperture: Specifies the aperture of the 32-bit BAR 0 or 64-bit BAR 0-1.The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR0_APERTURE_SIZE_30x000000088032rwNormal read/write0x00000000VF BAR0 Aperture: Specifies the aperture of the 32-bit BAR 0 or 64-bit BAR 0-1.The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR1_CONTROL_00x000000088432rwNormal read/write0x00000000VF BAR1 Control - Specifies the configuration of BAR 1 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR1_CONTROL_10x000000088832rwNormal read/write0x00000000VF BAR1 Control - Specifies the configuration of BAR 1 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR1_CONTROL_20x000000088C32rwNormal read/write0x00000000VF BAR1 Control - Specifies the configuration of BAR 1 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR1_CONTROL_30x000000089032rwNormal read/write0x00000000VF BAR1 Control - Specifies the configuration of BAR 1 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR1_APERTURE_SIZE_00x000000089432rwNormal read/write0x00000000VF BAR1 Aperture: Specifies the aperture of
BAR 1 when it is configured as a 32-bit BAR.
The valid encodings are:
00000-00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR1_APERTURE_SIZE_10x000000089832rwNormal read/write0x00000000VF BAR1 Aperture: Specifies the aperture of
BAR 1 when it is configured as a 32-bit BAR.
The valid encodings are:
00000-00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR1_APERTURE_SIZE_20x000000089C32rwNormal read/write0x00000000VF BAR1 Aperture: Specifies the aperture of
BAR 1 when it is configured as a 32-bit BAR.
The valid encodings are:
00000-00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR1_APERTURE_SIZE_30x00000008A032rwNormal read/write0x00000000VF BAR1 Aperture: Specifies the aperture of
BAR 1 when it is configured as a 32-bit BAR.
The valid encodings are:
00000-00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR2_CONTROL_00x00000008A432rwNormal read/write0x00000000VF BAR2 Control - Specifies the configuration of BAR 2.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_SRIOV_BAR2_CONTROL_10x00000008A832rwNormal read/write0x00000000VF BAR2 Control - Specifies the configuration of BAR 2.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_SRIOV_BAR2_CONTROL_20x00000008AC32rwNormal read/write0x00000000VF BAR2 Control - Specifies the configuration of BAR 2.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_SRIOV_BAR2_CONTROL_30x00000008B032rwNormal read/write0x00000000VF BAR2 Control - Specifies the configuration of BAR 2.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
0-1, non-prefetchable
111: Part of 64-bit memory BAR
0-1, prefetchable
PFx_SRIOV_BAR2_APERTURE_SIZE_00x00000008B432rwNormal read/write0x00000000VF BAR2 Aperture: Specifies the aperture of the 32-bit BAR 2 or 64-bit BAR2-3.
The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR2_APERTURE_SIZE_10x00000008B832rwNormal read/write0x00000000VF BAR2 Aperture: Specifies the aperture of the 32-bit BAR 2 or 64-bit BAR2-3.
The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR2_APERTURE_SIZE_20x00000008BC32rwNormal read/write0x00000000VF BAR2 Aperture: Specifies the aperture of the 32-bit BAR 2 or 64-bit BAR2-3.
The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR2_APERTURE_SIZE_30x00000008C032rwNormal read/write0x00000000VF BAR2 Aperture: Specifies the aperture of the 32-bit BAR 2 or 64-bit BAR2-3.
The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR3_CONTROL_00x00000008C432rwNormal read/write0x00000000VF BAR3 Control - Specifies the configuration of BAR 3 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR3_CONTROL_10x00000008C832rwNormal read/write0x00000000VF BAR3 Control - Specifies the configuration of BAR 3 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR3_CONTROL_20x00000008CC32rwNormal read/write0x00000000VF BAR3 Control - Specifies the configuration of BAR 3 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR3_CONTROL_30x00000008D032rwNormal read/write0x00000000VF BAR3 Control - Specifies the configuration of BAR 3 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR3_APERTURE_SIZE_00x00000008D432rwNormal read/write0x00000000VF BAR3 Aperture: Specifies the aperture of
BAR 3 when it is configured as a 32-bit BAR.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR3_APERTURE_SIZE_10x00000008D832rwNormal read/write0x00000000VF BAR3 Aperture: Specifies the aperture of
BAR 3 when it is configured as a 32-bit BAR.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR3_APERTURE_SIZE_20x00000008DC32rwNormal read/write0x00000000VF BAR3 Aperture: Specifies the aperture of
BAR 3 when it is configured as a 32-bit BAR.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR3_APERTURE_SIZE_30x00000008E032rwNormal read/write0x00000000VF BAR3 Aperture: Specifies the aperture of
BAR 3 when it is configured as a 32-bit BAR.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR4_CONTROL_00x00000008E432rwNormal read/write0x00000000VF BAR4 Control - Specifies the configuration of BAR 4.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
4-5, non-prefetchable
111: Part of 64-bit memory BAR
4-5, prefetchable
PFx_SRIOV_BAR4_CONTROL_10x00000008E832rwNormal read/write0x00000000VF BAR4 Control - Specifies the configuration of BAR 4.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
4-5, non-prefetchable
111: Part of 64-bit memory BAR
4-5, prefetchable
PFx_SRIOV_BAR4_CONTROL_20x00000008EC32rwNormal read/write0x00000000VF BAR4 Control - Specifies the configuration of BAR 4.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
4-5, non-prefetchable
111: Part of 64-bit memory BAR
4-5, prefetchable
PFx_SRIOV_BAR4_CONTROL_30x00000008F032rwNormal read/write0x00000000VF BAR4 Control - Specifies the configuration of BAR 4.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
110: Part of 64-bit memory BAR
4-5, non-prefetchable
111: Part of 64-bit memory BAR
4-5, prefetchable
PFx_SRIOV_BAR4_APERTURE_SIZE_00x00000008F432rwNormal read/write0x00000000VF BAR4 Aperture: Specifies the aperture of the 32-bit BAR 4 or 64-bit BAR4-5.
The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR4_APERTURE_SIZE_10x00000008F832rwNormal read/write0x00000000VF BAR4 Aperture: Specifies the aperture of the 32-bit BAR 4 or 64-bit BAR4-5.
The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR4_APERTURE_SIZE_20x00000008FC32rwNormal read/write0x00000000VF BAR4 Aperture: Specifies the aperture of the 32-bit BAR 4 or 64-bit BAR4-5.
The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR4_APERTURE_SIZE_30x000000090032rwNormal read/write0x00000000VF BAR4 Aperture: Specifies the aperture of the 32-bit BAR 4 or 64-bit BAR4-5.
The encodings are:
000000-000101 = 4 Kbytes
000110 = 8 Kbytes
000111 = 16 Kbytes
001000 = 32 Kbytes
001001 = 64 Kbytes
001010 = 128 Kbytes
001011 = 256 Kbytes
001100 = 512 Kbytes
001101 = 1 Mbytes
001110 = 2 Mbytes
001111 = 4 Mbytes
010000 = 8 Mbytes
010001 = 16 Mbytes
010010 = 32 Mbytes
010011 = 64 Mbytes
010100 = 128 Mbytes
010101 =
256 Mbytes
010110 = 512 Mbytes
010111 = 1 Gbytes
011000 = 2 Gbytes
011001 = 4 Gbytes
011010 = 8 Gbytes
011011 = 16 Gbytes
011100 = 32 Gbytes
011101 = 64 Gbytes
011110 = 128 Gbytes
011111 = 256 Gbytes
100000 = 512 Gbytes
100001= 1 Tbytes
100010= 2 Tbytes
100011 = 4 Tbytes
100100 = 8 Tbytes
100101 = 16 Tbytes
100110 = 32 Tbytes
100111 = 64 Tbytes
101000 = 128 Tbytes
101001 = 256 Tbytes
101010 = 512 Tbytes
101011= 1 Pbytes
101100= 2 Pbytes
101101 = 4 Pbytes
101110 = 8 Pbytes
101111 = 16 Pbytes
110000 = 32 Pbytes
110001 = 64 Pbytes
110010 = 128 Pbytes
110011 = 256 Pbytes
110100 = 512 Pbytes
110101= 1 Ebytes
110110= 2 Ebytes
110111 = 4 Ebytes
111000 = 8 Ebytes
PFx_SRIOV_BAR5_CONTROL_00x000000090432rwNormal read/write0x00000000VF BAR5 Control - Specifies the configuration of BAR 5 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR5_CONTROL_10x000000090832rwNormal read/write0x00000000VF BAR5 Control - Specifies the configuration of BAR 5 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR5_CONTROL_20x000000090C32rwNormal read/write0x00000000VF BAR5 Control - Specifies the configuration of BAR 5 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR5_CONTROL_30x000000091032rwNormal read/write0x00000000VF BAR5 Control - Specifies the configuration of BAR 5 when it is configured as a 32-bit BAR.
The various encodings are:
000: Disabled
001: 32-bit IO BAR
010-011: Reserved
100: 32-bit memory BAR, non-prefetchable
101: 32-bit memory BAR, prefetchable
PFx_SRIOV_BAR5_APERTURE_SIZE_00x000000091432rwNormal read/write0x00000000VF BAR5 Aperture: Specifies the aperture of
BAR 5 when it is configured as a 32-bit BAR.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR5_APERTURE_SIZE_10x000000091832rwNormal read/write0x00000000VF BAR5 Aperture: Specifies the aperture of
BAR 5 when it is configured as a 32-bit BAR.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR5_APERTURE_SIZE_20x000000091C32rwNormal read/write0x00000000VF BAR5 Aperture: Specifies the aperture of
BAR 5 when it is configured as a 32-bit BAR.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
PFx_SRIOV_BAR5_APERTURE_SIZE_30x000000092032rwNormal read/write0x00000000VF BAR5 Aperture: Specifies the aperture of
BAR 5 when it is configured as a 32-bit BAR.
The valid encodings are:
00000 = 128bytes
00001 = 256bytes
00010 = 512bytes
00011 = 1 Kbytes
00100 = 2 Kbytes
00101 = 4 Kbytes
00110 = 8 Kbytes
00111 = 16 Kbytes
01000 = 32 Kbytes
01001 = 64 Kbytes
01010 = 128 Kbytes
01011 = 256 Kbytes
01100 = 512 Kbytes
01101 = 1 Mbytes
01110 = 2 Mbytes
01111 = 4 Mbytes
10000 = 8 Mbytes
10001 = 16 Mbytes
10010 = 32 Mbytes
10011 = 64 Mbytes
10100 = 128 Mbytes
10101 =
256 Mbytes
10110 = 512 Mbytes
10111 = 1 Gbytes
11000 = 2 Gbytes
zFx_TPHR_CAP_NEXTPTR_00x000000092432rwNormal read/write0x00000000TPHR Next Capability Offset: Bits 31:20 TPHR Extended Capability Header Register. Only lower 8 bits are in use.
zFx_TPHR_CAP_NEXTPTR_10x000000092832rwNormal read/write0x00000000TPHR Next Capability Offset: Bits 31:20 TPHR Extended Capability Header Register. Only lower 8 bits are in use.
zFx_TPHR_CAP_NEXTPTR_20x000000092C32rwNormal read/write0x00000000TPHR Next Capability Offset: Bits 31:20 TPHR Extended Capability Header Register. Only lower 8 bits are in use.
zFx_TPHR_CAP_NEXTPTR_30x000000093032rwNormal read/write0x00000000TPHR Next Capability Offset: Bits 31:20 TPHR Extended Capability Header Register. Only lower 8 bits are in use.
zFx_TPHR_CAP_NEXTPTR_40x000000093432rwNormal read/write0x00000000TPHR Next Capability Offset: Bits 31:20 TPHR Extended Capability Header Register. Only lower 8 bits are in use.
zFx_TPHR_CAP_NEXTPTR_50x000000093832rwNormal read/write0x00000000TPHR Next Capability Offset: Bits 31:20 TPHR Extended Capability Header Register. Only lower 8 bits are in use.
zFx_TPHR_CAP_NEXTPTR_60x000000093C32rwNormal read/write0x00000000TPHR Next Capability Offset: Bits 31:20 TPHR Extended Capability Header Register. Only lower 8 bits are in use.
zFx_TPHR_CAP_NEXTPTR_70x000000094032rwNormal read/write0x00000000TPHR Next Capability Offset: Bits 31:20 TPHR Extended Capability Header Register. Only lower 8 bits are in use.
PF0_TPHR_CAP_VER0x000000094432rwNormal read/write0x00000000TPHR Capability Version: Bits 19:16 TPHR Extended Capability Header Register. All PFs and VFs
PF0_TPHR_CAP_INT_VEC_MODE0x000000094832rwNormal read/write0x00000000Interrupt Vector Mode Supported: Bit 1 in TPH Requester Capability Register. A Setting of TRUE indicates that the Function supports the Interrupt Vector Mode for TPH Steering Tag generation. In the Interrupt Vector Mode, Steering Tags are attached to MSI/MSI-X interrupt requests. The Steering Tag for each interrupt request is selected by the MSI/MSI-X interrupt vector number.
PF0_TPHR_CAP_DEV_SPECIFIC_MODE0x000000094C32rwNormal read/write0x00000000Device Specific Mode Supported: Bit 2 in TPH Requester Capability Register. A setting of TRUE indicates that the Function supports the Device-Specific Mode for TPH Steering Tag generation. In this mode, the Steering Tags are supplied by the client for each request through the AXI interface. The client typically choses the Steering Tag values from the ST Table, but is not required to do so.
PF0_TPHR_CAP_ST_TABLE_LOC0x000000095032rwNormal read/write0x00000000Steering Tag (ST) Table Location: Bits 10:0 in TPH Requester Capability Register. The setting of this field indicates if a Steering Tag Table is implemented for this Function, and its location if present. 00b => ST Table not present, 01b => ST Table in the TPH Requester Capability Structure, 10b => ST values stored in the MSI-X Table in used memory space (reserved), 11b => is reserved.
PF0_TPHR_CAP_ST_TABLE_SIZE0x000000095432rwNormal read/write0x00000000Steering Tag (ST) Table Size
Sets bits 26:16 in TPH Requester Capability Register. Value indicates the maximum number of ST Table entries the Function may use. Software reads this field to determine the ST Table Size N, which is encoded as N-1.
There is an upper limit of 64 entries when the ST Table is located in the TPH Requester Capability structure. Supported Table Size values are 16, 32 and 64
PF0_TPHR_CAP_ENABLE0x000000097832rwNormal read/write0x00000000TPH Requester Enable:
When TRUE enables TPHR Capability on all PFs and VFs
TPH_TO_RAM_PIPELINE0x000000097C32rwNormal read/write0x00000000TPH
To RAM Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on the Hard Block to BRAM path. FALSE indicates that there is no pipeline.
TPH_FROM_RAM_PIPELINE0x000000098032rwNormal read/write0x00000000TPH From RAM Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline
stage on BRAM to Hard Block path. FALSE indicates that there is no pipeline.
zFx_ATS_CAP_ON_00x000000098432rwNormal read/write0x00000000ATS Capability Enable
zFx_ATS_CAP_ON_10x000000098832rwNormal read/write0x00000000ATS Capability Enable
zFx_ATS_CAP_ON_20x000000098C32rwNormal read/write0x00000000ATS Capability Enable
zFx_ATS_CAP_ON_30x000000099032rwNormal read/write0x00000000ATS Capability Enable
zFx_ATS_CAP_ON_40x000000099432rwNormal read/write0x00000000ATS Capability Enable
zFx_ATS_CAP_ON_50x000000099832rwNormal read/write0x00000000ATS Capability Enable
zFx_ATS_CAP_ON_60x000000099C32rwNormal read/write0x00000000ATS Capability Enable
zFx_ATS_CAP_ON_70x00000009A032rwNormal read/write0x00000000ATS Capability Enable
zFx_ATS_CAP_NEXTPTR_00x00000009A432rwNormal read/write0x00000000ATS Capability Next Pointer
zFx_ATS_CAP_NEXTPTR_10x00000009A832rwNormal read/write0x00000000ATS Capability Next Pointer
zFx_ATS_CAP_NEXTPTR_20x00000009AC32rwNormal read/write0x00000000ATS Capability Next Pointer
zFx_ATS_CAP_NEXTPTR_30x00000009B032rwNormal read/write0x00000000ATS Capability Next Pointer
zFx_ATS_CAP_NEXTPTR_40x00000009B432rwNormal read/write0x00000000ATS Capability Next Pointer
zFx_ATS_CAP_NEXTPTR_50x00000009B832rwNormal read/write0x00000000ATS Capability Next Pointer
zFx_ATS_CAP_NEXTPTR_60x00000009BC32rwNormal read/write0x00000000ATS Capability Next Pointer
zFx_ATS_CAP_NEXTPTR_70x00000009C032rwNormal read/write0x00000000ATS Capability Next Pointer
zFx_ATS_CAP_INV_QUEUE_DEPTH_00x00000009C432rwNormal read/write0x00000000ATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED
zFx_ATS_CAP_INV_QUEUE_DEPTH_10x00000009C832rwNormal read/write0x00000000ATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED
zFx_ATS_CAP_INV_QUEUE_DEPTH_20x00000009CC32rwNormal read/write0x00000000ATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED
zFx_ATS_CAP_INV_QUEUE_DEPTH_30x00000009D032rwNormal read/write0x00000000ATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED
zFx_ATS_CAP_INV_QUEUE_DEPTH_40x00000009D432rwNormal read/write0x00000000ATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED
zFx_ATS_CAP_INV_QUEUE_DEPTH_50x00000009D832rwNormal read/write0x00000000ATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED
zFx_ATS_CAP_INV_QUEUE_DEPTH_60x00000009DC32rwNormal read/write0x00000000ATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED
zFx_ATS_CAP_INV_QUEUE_DEPTH_70x00000009E032rwNormal read/write0x00000000ATS Capability Invalidate Queue Depth
VFG* attributes are UNUSED
PFx_PRI_CAP_ON_00x00000009E432rwNormal read/write0x00000000PRI Capability Enable
PFx_PRI_CAP_ON_10x00000009E832rwNormal read/write0x00000000PRI Capability Enable
PFx_PRI_CAP_ON_20x00000009EC32rwNormal read/write0x00000000PRI Capability Enable
PFx_PRI_CAP_ON_30x00000009F032rwNormal read/write0x00000000PRI Capability Enable
PFx_PRI_CAP_NEXTPTR_00x00000009F432rwNormal read/write0x00000000PRI Capability Next Pointer
PFx_PRI_CAP_NEXTPTR_10x00000009F832rwNormal read/write0x00000000PRI Capability Next Pointer
PFx_PRI_CAP_NEXTPTR_20x00000009FC32rwNormal read/write0x00000000PRI Capability Next Pointer
PFx_PRI_CAP_NEXTPTR_30x0000000A0032rwNormal read/write0x00000000PRI Capability Next Pointer
PFx_PRI_OST_PR_CAPACITY_00x0000000A0432rwNormal read/write0x00000000PRI Outstanding Page Request Capacity
PFx_PRI_OST_PR_CAPACITY_10x0000000A0832rwNormal read/write0x00000000PRI Outstanding Page Request Capacity
PFx_PRI_OST_PR_CAPACITY_20x0000000A0C32rwNormal read/write0x00000000PRI Outstanding Page Request Capacity
PFx_PRI_OST_PR_CAPACITY_30x0000000A1032rwNormal read/write0x00000000PRI Outstanding Page Request Capacity
CCIX_ENABLE0x0000000A1432rwNormal read/write0x00000000CCIX Enable: Enables CCIX Features (across the board)
CCIX_OPT_TLP_GEN_AND_RECEPT_EN_CONTROL_INTERNAL0x0000000A1832rwNormal read/write0x00000000CCIX Optimized TLP Generation and Reception Enable Control Internal: When TRUE, control with Transport DVSEC, Transaction Control Register, Enable Optimized TLP Generation and Reception bit. This must be set to 1.
CCIX_VENDOR_ID0x0000000A1C32rwNormal read/write0x00000000CCIX Vendor ID
CCIX_TRANSPORT_PF0_DVSEC_ENABLE0x0000000A2032rwNormal read/write0x00000000CCIX Transport DVSEC Enable: In PCIe Block A, when TRUE enables Transport DVSEC in PF0. When FALSE disables Transport DVSEC in PF0.
CCIX_PROTOCOL_PF0_DVSEC_ENABLE0x0000000A2432rwNormal read/write0x00000000CCIX Protocol DVSEC in PF0 Enable: In PCIe Block A, when TRUE enables Protocol
DVSEC in PF0. When FALSE disables Protocol DVSEC in PF1.
CCIX_PROTOCOL_PF1_DVSEC_ENABLE0x0000000A2832rwNormal read/write0x00000000CCIX Protocol DVSEC in PF1 Enable: In PCIe Block A, when TRUE enables Protocol DVSEC in PF1. When FALSE disables Protocol DVSEC in PF1.
CCIX_CFG_MGMT_MUX_ENABLE0x0000000A2C32rwNormal read/write0x00000000CCIX Cfg Management Mux Enable: In PCIe Block A, when TRUE enables Cfg Management Mux. When FALSE disables Cfg Management Mux (bypass mode).
CCIX_TX_CREDIT_CHECK_DISABLE0x0000000A3032rwNormal read/write0x00000000CCIX TL Tx Credit Check Disable: When set to FALSE,
CXS state machine in De-Active state will wait for all the credits to be returned to the DUT before going to STOP state. When set to TRUE, CXS state machine in De-Active state will wait for a set time of <30>
CXS interface clk cycles (ignoring the credit return) before moving to STOP state.
PF0_CCIX_TDVSEC_CAP_NEXTPTR0x0000000A3432rwNormal read/write0x00000000PF0 CCIX Transport DVSEC Next Pointer
PF0_CCIX_TDVSEC_CAP_VENDOR_ID0x0000000A3832rwNormal read/write0x00000000PF0 CCIX Transport DVSEC Capability ID
PF0_CCIX_TDVSEC_CAP_REVISION0x0000000A3C32rwNormal read/write0x00000000PF0 CCIX Transport DVSEC Revision ID
PF0_CCIX_TDVSEC_CAP_LENGTH0x0000000A4032rwNormal read/write0x00000000PF0 CCIX Transport DVSEC Length
PF0_CCIX_TDVSEC_CAP_ID0x0000000A4432rwNormal read/write0x00000000PF0 CCIX Transport DVSEC Vendor ID
PF0_CCIX_TDVSEC_CCIX_VC_BYTE_OFFSET0x0000000A4832rwNormal read/write0x00000000PF0 CCIX Transport DVSEC VC Resource Byte Offset. This register must be programmed to 0x01 when CCIX is enabled on VC1.
CCIX_DIRECT_ATTACH_MODE0x0000000A4C32rwNormal read/write0x00000000CCIX Direct Attach Mode:
PF0_CCIX_ESM_QUICK_EQ_TIMEOUT0x0000000A5032rwNormal read/write0x00000000PF0 CCIX Transport DVSEC Quick EQ Timeout
PF0_CCIX_PDVSEC_CAP_NEXTPTR0x0000000A5432rwNormal read/write0x00000000PF0 CCIX Protocol DVSEC Next Pointer
PF0_CCIX_PDVSEC_CAP_VENDOR_ID0x0000000A5832rwNormal read/write0x00000000PF0 CCIX Protocol DVSECVendor ID
PF0_CCIX_PDVSEC_CAP_REVISION0x0000000A5C32rwNormal read/write0x00000000PF0 CCIX Protocol DVSEC Revision ID
PF0_CCIX_PDVSEC_CAP_LENGTH0x0000000A6032rwNormal read/write0x00000000PF0 CCIX Protocol DVSEC Length
PF0_CCIX_PDVSEC_CAP_ID0x0000000A6432rwNormal read/write0x00000000PF0 CCIX Protocol DVSEC Capability ID
PF0_CCIX_PDVSEC_PCSR_START_ADDR0x0000000A6832rwNormal read/write0x00000000PF0 CCIX Protocol DVSEC CSR Region Start Address
PF0_CCIX_PDVSEC_PCSR_SIZE0x0000000A6C32rwNormal read/write0x00000000PF0 CCIX Protocol DVSEC CSR Region Size
PF0_CCIX_PDVSEC_PCR_START_ADDR0x0000000A7032rwNormal read/write0x00000000PF0 CCIX Protocol DVSEC CR Region Start Address
PF0_CCIX_PDVSEC_PCR_SIZE0x0000000A7432rwNormal read/write0x00000000PF0 CCIX Protocol DVSEC CR Region Size
PF1_CCIX_PDVSEC_CAP_NEXTPTR0x0000000A7832rwNormal read/write0x00000000PF1 CCIX Protocol DVSEC Next Pointer
PF1_CCIX_PDVSEC_CAP_VENDOR_ID0x0000000A7C32rwNormal read/write0x00000000PF1 CCIX Protocol DVSECVendor ID
PF1_CCIX_PDVSEC_CAP_REVISION0x0000000A8032rwNormal read/write0x00000000PF1 CCIX Protocol DVSEC Revision ID
PF1_CCIX_PDVSEC_CAP_LENGTH0x0000000A8432rwNormal read/write0x00000000PF1 CCIX Protocol DVSEC Length
PF1_CCIX_PDVSEC_CAP_ID0x0000000A8832rwNormal read/write0x00000000PF1 CCIX Protocol DVSEC Capability ID
PF1_CCIX_PDVSEC_PCSR_START_ADDR0x0000000A8C32rwNormal read/write0x00000000PF1 CCIX Protocol DVSEC CSR Region Start Address
PF1_CCIX_PDVSEC_PCSR_SIZE0x0000000A9032rwNormal read/write0x00000000PF1 CCIX Protocol DVSEC CSR Region Size
PF1_CCIX_PDVSEC_PCR_START_ADDR0x0000000A9432rwNormal read/write0x00000000PF1 CCIX Protocol DVSEC CR Region Start Address
PF1_CCIX_PDVSEC_PCR_SIZE0x0000000A9832rwNormal read/write0x00000000PF1 CCIX Protocol DVSEC CR Region Size
CCIX_PDVSEC_CPL_TIMEOUT0x0000000A9C32rwNormal read/write0x00000000CCIX Protocol DVSEC Completion Timeout
PF0_DEV_CAP2_10B_TAG_REQUESTER_SUPPORTED0x0000000AA032rwNormal read/write0x0000000010-Bit Tag Requester Supported: When TRUE all Functions supports 10-Bit Tag Requester capability; otherwise, the Functions do not. Can be TRUE only if PF0_DEV_CAP2_10B_TAG_COMPLETER_SUPPORTED must be TRUE.
PF0_DEV_CAP2_10B_TAG_COMPLETER_SUPPORTED0x0000000AA432rwNormal read/write0x0000000010-Bit Tag Completer Supported: When TRUE
all Functions supports 10-Bit Tag Completer capability; otherwise, the Functions do not.
VFGx_10B_TAG_REQUESTER_SUPPORTED_00x0000000AA832rwNormal read/write0x00000000VF 10-Bit Tag Completer Supported: When TRUE
all VFs associated with the PF must support 10-Bit Tag Requester capability. If Clear, VFs associated with PF must not support 10-Bit Tag Requester capability (in SRIOV Cap).
VFGx_10B_TAG_REQUESTER_SUPPORTED_10x0000000AAC32rwNormal read/write0x00000000VF 10-Bit Tag Completer Supported: When TRUE
all VFs associated with the PF must support 10-Bit Tag Requester capability. If Clear, VFs associated with PF must not support 10-Bit Tag Requester capability (in SRIOV Cap).
VFGx_10B_TAG_REQUESTER_SUPPORTED_20x0000000AB032rwNormal read/write0x00000000VF 10-Bit Tag Completer Supported: When TRUE
all VFs associated with the PF must support 10-Bit Tag Requester capability. If Clear, VFs associated with PF must not support 10-Bit Tag Requester capability (in SRIOV Cap).
VFGx_10B_TAG_REQUESTER_SUPPORTED_30x0000000AB432rwNormal read/write0x00000000VF 10-Bit Tag Completer Supported: When TRUE
all VFs associated with the PF must support 10-Bit Tag Requester capability. If Clear, VFs associated with PF must not support 10-Bit Tag Requester capability (in SRIOV Cap).
PF0_PL16_CAP_ON0x0000000AB832rwNormal read/write0x00000000DLL Feature Cap On
PF0_PL16_CAP_NEXTPTR0x0000000ABC32rwNormal read/write0x00000000DLL Feature Cap Next Pointer
PF0_PL16_CAP_VER0x0000000AC032rwNormal read/write0x00000000DLL Feature Cap Version
PF0_PL16_CAP_ID0x0000000AC432rwNormal read/write0x00000000DLL Feature Cap ID
PF0_MARGINING_CAP_ON0x0000000AC832rwNormal read/write0x00000000Margining Cap On
PF0_MARGINING_CAP_NEXTPTR0x0000000ACC32rwNormal read/write0x00000000Margining Cap Next Pointer
PF0_MARGINING_CAP_VER0x0000000AD032rwNormal read/write0x00000000Margining Cap Version
PF0_MARGINING_CAP_ID0x0000000AD432rwNormal read/write0x00000000Margining Cap ID
PF0_MARGINING_USES_DRVR_SW0x0000000AD832rwNormal read/write0x00000000Margining Uses Driver Software
PF0_DLL_FEATURE_CAP_ON0x0000000ADC32rwNormal read/write0x00000000DLL Feature Cap On
PFx_DLL_FEATURE_CAP_NEXTPTR_00x0000000AE032rwNormal read/write0x00000000DLL Feature Cap Next Pointer
PFx_DLL_FEATURE_CAP_NEXTPTR_10x0000000AE432rwNormal read/write0x00000000DLL Feature Cap Next Pointer
PFx_DLL_FEATURE_CAP_NEXTPTR_20x0000000AE832rwNormal read/write0x00000000DLL Feature Cap Next Pointer
PFx_DLL_FEATURE_CAP_NEXTPTR_30x0000000AEC32rwNormal read/write0x00000000DLL Feature Cap Next Pointer
PF0_DLL_FEATURE_CAP_VER0x0000000AF032rwNormal read/write0x00000000DLL Feature Cap Version
PF0_DLL_FEATURE_CAP_ID0x0000000AF432rwNormal read/write0x00000000DLL Feature Cap ID
PF0_PASID_CAP_ON0x0000000AF832rwNormal read/write0x00000000PASID Feature Cap On
PFx_PASID_CAP_NEXTPTR_00x0000000AFC32rwNormal read/write0x00000000PASID Feature Cap Next Pointer
PFx_PASID_CAP_NEXTPTR_10x0000000B0032rwNormal read/write0x00000000PASID Feature Cap Next Pointer
PFx_PASID_CAP_NEXTPTR_20x0000000B0432rwNormal read/write0x00000000PASID Feature Cap Next Pointer
PFx_PASID_CAP_NEXTPTR_30x0000000B0832rwNormal read/write0x00000000PASID Feature Cap Next Pointer
PFx_PASID_CAP_EXEC_PERM_SUPP_00x0000000B0C32rwNormal read/write0x00000000PASID support for sending TLPS with Execute Requested bit.
PFx_PASID_CAP_EXEC_PERM_SUPP_10x0000000B1032rwNormal read/write0x00000000PASID support for sending TLPS with Execute Requested bit.
PFx_PASID_CAP_EXEC_PERM_SUPP_20x0000000B1432rwNormal read/write0x00000000PASID support for sending TLPS with Execute Requested bit.
PFx_PASID_CAP_EXEC_PERM_SUPP_30x0000000B1832rwNormal read/write0x00000000PASID support for sending TLPS with Execute Requested bit.
PFx_PASID_CAP_PRIVIL_MODE_SUPP_00x0000000B1C32rwNormal read/write0x00000000PASID support for sending TLPs with Priviledge Mode Requested bit.
PFx_PASID_CAP_PRIVIL_MODE_SUPP_10x0000000B2032rwNormal read/write0x00000000PASID support for sending TLPs with Priviledge Mode Requested bit.
PFx_PASID_CAP_PRIVIL_MODE_SUPP_20x0000000B2432rwNormal read/write0x00000000PASID support for sending TLPs with Priviledge Mode Requested bit.
PFx_PASID_CAP_PRIVIL_MODE_SUPP_30x0000000B2832rwNormal read/write0x00000000PASID support for sending TLPs with Priviledge Mode Requested bit.
PFx_PASID_CAP_MAX_PASID_WIDTH_00x0000000B2C32rwNormal read/write0x00000000Max PASID Width. Permitted to be in the range 0D (single PASID) to 20D (all PASID value (20 bits))
PFx_PASID_CAP_MAX_PASID_WIDTH_10x0000000B3032rwNormal read/write0x00000000Max PASID Width. Permitted to be in the range 0D (single PASID) to 20D (all PASID value (20 bits))
PFx_PASID_CAP_MAX_PASID_WIDTH_20x0000000B3432rwNormal read/write0x00000000Max PASID Width. Permitted to be in the range 0D (single PASID) to 20D (all PASID value (20 bits))
PFx_PASID_CAP_MAX_PASID_WIDTH_30x0000000B3832rwNormal read/write0x00000000Max PASID Width. Permitted to be in the range 0D (single PASID) to 20D (all PASID value (20 bits))
MCAP_ENABLE0x0000000B3C32rwNormal read/write0x00000000MCAP Enable: Enabled MCAP Vendor Specific Capability Structure in Function #0. This feature is supported only in the Legacy Endpoint and Endpoint modes. When MCAP_ENABLE is false, all other MCAP_* attributes that are boolean must be set to FALSE and value of 0 driven on non boolean attributes.
MCAP_CAP_NEXTPTR0x0000000B4432rwNormal read/write0x00000000MCAP
Next Capability Offset: Bits 31:20 MCAP Extended Capability Header Register
MCAP_VSEC_ID0x0000000B4832rwNormal read/write0x00000000MCAP VSEC ID: This field is a vendor-defined ID number that indicates the nature and format of the VSEC structure.
MCAP_VSEC_REV0x0000000B4C32rwNormal read/write0x00000000MCAP VSEC Rev: This field is a vendor-defined version number that indicates the version of the VSEC structure.
MCAP_VSEC_LEN0x0000000B5032rwNormal read/write0x00000000MCAP VSEC Length: This field indicates the number of bytes in the entire VSEC structure, including the PCI Express Extended Capability header, the Vendor- Specific header, and the Vendor-Specific registers.
DEBUG_AXIST_DISABLE_FEATURE_BIT0x0000000B7432rwNormal read/write0x00000000AXIST Feature Disable Bits. Each bit is associated with an AXIST feature which can be disabled by setting it to 1.
Bit[0]: Disable RC Invalid Tag checking
Bit[1]: Disable RC Poisoned checking
Bit[2]: Disable RC RID Mismatch checking
Bit[3]: Disable RC TC/AT Mismatch checking
Bit[4]: Disable RC Address Mismatch checking
Bit[5]: Disable RC Byte Count checking
Bit[6]: Disable RC Completion Status checking
Bit[7]: Disable CQ BAR Hit checking. The incoming TLPs always hit PF0.
DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS0x0000000B7832rwNormal read/write0x00000000When TRUE, disables the required PCIe ordering rule check between received Completions and Posted requests.
DEBUG_TL_DISABLE_FC_TIMEOUT0x0000000B7C32rwNormal read/write0x00000000When TRUE, disables link retrain due to FC Timeout Disable
DEBUG_PL_DISABLE_SCRAMBLING0x0000000B8032rwNormal read/write0x00000000When TRUE, disables scrabler and de-scrambler in the Physical Layer at Gen1/2 speeds. Used for test and debug only.
DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FLD0x0000000B8432rwNormal read/write0x00000000When set to FALSE, a dynamic deskew failure will cause Recovery, otherwise, if set to TRUE, dynamic deskew failure will be ignored. Should be set to FALSE on Asynchronous Links. May have to be set to TRUE on Synchronous Link with BER to avoid unnecessary transitions to Recovery.
DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR0x0000000B8C32rwNormal read/write0x00000000When set to FALSE, allows to not update the Lane Error Status register on SKP error detection.
DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR0x0000000B9432rwNormal read/write0x00000000When set to FALSE, allows to not update the Lane Error Status register on Deframer error detection.
DEBUG_PL_SIM_RESET_LFSR0x0000000B9832rwNormal read/write0x00000000When set to TRUE, used in simulation only, to reset Gen3,4 LFSRs to seed value or reset Gen1/2 LFSR to reset value
DEBUG_PL_SPARE0x0000000B9C32rwNormal read/write0x00000000PL Debug Spare Bits
DEBUG_LL_SPARE0x0000000BA032rwNormal read/write0x00000000LL Debug Spare Bits
DEBUG_TL_SPARE0x0000000BA432rwNormal read/write0x00000000TL Debug Spare Bits
DEBUG_AXI4ST_SPARE0x0000000BA832rwNormal read/write0x00000000AXI4ST
Debug Spare Bits
DEBUG_CFG_SPARE0x0000000BAC32rwNormal read/write0x00000000CFG
Debug Spare Bits
DEBUG_CAR_SPARE0x0000000BB032rwNormal read/write0x00000000CAR
Debug Spare Bits
DEBUG_NO_STICKY_RESET0x0000000BB432rwNormal read/write0x00000000When set to TRUE, sticky register bits will be preserved through warm/hot/link down reset.
TEST_MODE_PIN_CHAR0x0000000BB832rwNormal read/write0x00000000Pin Characterization Test mode. When TRUE enable Input to Output paths for pin characterization. Note: pipe_txn/rxn_data[15:0] (only) are testable with the following configuration required: CRM_CORE_CLK_FREQ_500 = "FALSE", pipe_clk = 125MHz, core_clk = 250MHz.
SPARE_BIT00x0000000BBC32rwNormal read/write0x00000000Spare attribute
SPARE_BIT10x0000000BC032rwNormal read/write0x00000000Spare attribute
SPARE_BIT20x0000000BC432rwNormal read/write0x00000000Spare attribute
SPARE_BIT30x0000000BC832rwNormal read/write0x00000000Spare attribute
SPARE_BIT40x0000000BCC32rwNormal read/write0x00000000Spare attribute
SPARE_BIT50x0000000BD032rwNormal read/write0x00000000Spare attribute
SPARE_BIT60x0000000BD432rwNormal read/write0x00000000Spare attribute
SPARE_BIT70x0000000BD832rwNormal read/write0x00000000Spare attribute
SPARE_BIT80x0000000BDC32rwNormal read/write0x00000000Spare attribute
SPARE_BYTE00x0000000BE032rwNormal read/write0x00000000Spare attribute
SPARE_BYTE10x0000000BE432rwNormal read/write0x00000000Spare attribute
SPARE_BYTE20x0000000BE832rwNormal read/write0x00000000Spare attribute
SPARE_BYTE30x0000000BEC32rwNormal read/write0x00000000Spare attribute
SPARE_WORD00x0000000BF032rwNormal read/write0x00000000Spare attribute
SPARE_WORD10x0000000BF432rwNormal read/write0x00000000Spare attribute
SPARE_WORD20x0000000BF832rwNormal read/write0x00000000Spare attribute
SPARE_WORD30x0000000BFC32rwNormal read/write0x00000000Spare attribute
USER_TPH0x0000000E0032mixedMixed types. See bit-field details.0x00000000USER_TPH
PCIE_PL0x0000000E0432mixedMixed types. See bit-field details.0x00000000PCIE_PL
cfg_dsn_low0x0000000E0832rwNormal read/write0x00000000cfg_dsn_low
cfg_dsn_high0x0000000E0C32rwNormal read/write0x00000000cfg_dsn_high
cfg_dev_id_pf00x0000000E1032rwNormal read/write0x00000000cfg_dev_id_pf0
cfg_dev_id_pf10x0000000E1432rwNormal read/write0x00000000cfg_dev_id_pf1
cfg_dev_id_pf20x0000000E1832rwNormal read/write0x00000000cfg_dev_id_pf2
cfg_dev_id_pf30x0000000E1C32rwNormal read/write0x00000000cfg_dev_id_pf3
cfg_vend_id0x0000000E2032rwNormal read/write0x00000000cfg_vend_id
cfg_rev_id_pf00x0000000E2432rwNormal read/write0x00000000cfg_rev_id_pf0
cfg_rev_id_pf10x0000000E2832rwNormal read/write0x00000000cfg_rev_id_pf1
cfg_rev_id_pf20x0000000E2C32rwNormal read/write0x00000000cfg_rev_id_pf2
cfg_rev_id_pf30x0000000E3032rwNormal read/write0x00000000cfg_rev_id_pf3
cfg_subsys_id_pf00x0000000E3432rwNormal read/write0x00000000cfg_subsys_id_pf0
cfg_subsys_id_pf10x0000000E3832rwNormal read/write0x00000000cfg_subsys_id_pf1
cfg_subsys_id_pf20x0000000E3C32rwNormal read/write0x00000000cfg_subsys_id_pf2
cfg_subsys_id_pf30x0000000E4032rwNormal read/write0x00000000cfg_subsys_id_pf3
cfg_subsys_vend_id0x0000000E4432rwNormal read/write0x00000000cfg_subsys_vend_id
cfg_ds_port_number0x0000000E4832rwNormal read/write0x00000000cfg_ds_port_number
cfg_ds_bus_number0x0000000E4C32rwNormal read/write0x00000000cfg_ds_bus_number
cfg_ds_device_number0x0000000E5032rwNormal read/write0x00000000cfg_ds_device_number
cfg_ds_function_number0x0000000E5432rwNormal read/write0x00000000cfg_ds_function_number
cfg_req_pm_transition_l23_ready0x0000000E5832rwNormal read/write0x00000000cfg_req_pm_transition_l23_ready
cfg_link_training_enable0x0000000E5C32rwNormal read/write0x00000000cfg_link_training_enable
cfg_pm_aspm_l1_entry_reject0x0000000E6032rwNormal read/write0x00000000cfg_pm_aspm_l1_entry_reject
cfg_pm_aspm_tx_l0s_entry_disable0x0000000E6432rwNormal read/write0x00000000cfg_pm_aspm_tx_l0s_entry_disable
cfg_config_space_enable0x0000000E6832rwNormal read/write0x00000000cfg_config_space_enable
cfg_bus_number0x0000000E6C32roRead-only0x00000000cfg_bus_number
DPLL_CTRL_STATUS0x0000000E7032mixedMixed types. See bit-field details.0x00000000Control and Status for DPLL in PL
CPM_PCIE_DBG0x0000000E7432rwNormal read/write0x00000000CPM_PCIE_DBG
cfg0x0000000E7832mixedMixed types. See bit-field details.0x00000000cfg
dpll_sm_timeout0x0000000E7C32rwNormal read/write0x000007D0dpll_sm_timeout
dpll0x0000000E8032rwNormal read/write0x00000002dpll
fabricen0x0000000E8432rwNormal read/write0x00000000Fabricen for independent isolation for a PCIe Core. Fabricen=0: isolation enabled, Fabricen=1: no isolation
ccix_optimized_tlp_tx_and_rx_enable0x0000000E8832rwNormal read/write0x00000000CCIX register implemented instead of PL pin
cfg_interrupt0x0000000E8C32mixedMixed types. See bit-field details.0x00000000cfg_interrupt
phy_rdy0x0000000E9032roRead-only0x00000000phy_rdy
div_override0x0000000E9432rwNormal read/write0x00000000XPIPE clock divider override register for PL loop back mode (IMPORTANT NOTE: Make sure only 1 field of this register is changed with each configuration write)
pcie_cfg_msg0x0000000E9832mixedMixed types. See bit-field details.0x00000000pcie_cfg_msg
cfg_vc1_negotiation_pending0x0000000E9C32roRead-only0x00000000cfg_vc1_negotiation_pending