CCIX_PER_MESSAGE_CAP_ENABLE (CPM5_PCIE_ATTR) Register Description
| Register Name | CCIX_PER_MESSAGE_CAP_ENABLE |
|---|---|
| Offset Address | 0x0000001DF0 |
| Absolute Address |
0x00FCE09DF0 (CPM5_PCIE0_ATTR) 0x00FCE89DF0 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | CCIX PER Message Capability Structure Enable: When set to TRUE, enables the PER Message Capability at 0x3f0 byte address in PF0. When FALSE disables PER Message Capability in PF0. |
This register should only be written to during reset of the PCIe block
CCIX_PER_MESSAGE_CAP_ENABLE (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 |