AXISTEN_IF_RC_ALIGNMENT_MODE (CPM4_PCIE0_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

AXISTEN_IF_RC_ALIGNMENT_MODE (CPM4_PCIE0_ATTR) Register Description

Register NameAXISTEN_IF_RC_ALIGNMENT_MODE
Offset Address0x000000005C
Absolute Address 0x00FCA5005C (CPM4_PCIE0_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAXI Streaming Enhanced Inteface RC Alignment:
Determines the data alignment mode for the RC interface: 00b = Dword-aligned mode, 01b = 256b-address-aligned mode,
10b = 128b-address-aligned mode, 11b = Reserved. Encoding 10b is suppored only when
AXISTEN_IF_EXT_512=TRUE. Encoding 01b is not suppored only when
AXISTEN_IF_EXT_512=TRUE. Encodings 01b and 10b can used only if AXISTEN_IF_RQ_ALIGNMENT_MODE is set to 01b or 10b.

This register should only be written to during reset of the PCIe block

AXISTEN_IF_RC_ALIGNMENT_MODE (CPM4_PCIE0_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 1:0rwNormal read/write0x0