AXIBar_Highaddr_5_L (CPM4_DMA_ATTR) Register - AM012

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2024-08-19
Revision
1.4

AXIBar_Highaddr_5_L (CPM4_DMA_ATTR) Register Description

Register NameAXIBar_Highaddr_5_L
Offset Address0x000000018C
Absolute Address 0x00FCA7018C (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAXI to PCIe bar high address

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_axibar_highaddr_5_l

AXIBar_Highaddr_5_L (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x0