XRAM Register Sets

XRAM Register Sets - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2025-03-11

Revision

1.7 English

The XRAM includes several types of registers.

XRAM_SLCR Registers

The SLCR registers provide control and status for the clock, reset, request, status, TrustZone, and interrupt signals.

Table 1. XRAM_SLCR Register Set
Register Name	Access Type	Description
PCSR_MASK PCSR_PCR PCSR_PSR PCSR_LOCK
MAIN_CLK	RW	Select main clock source
APB_CLK	RW	Select programming interface clock source
RST	RW	Select external reset source
PWR_UP_BANKx	W	Power up control
PWR_DOWN_BANKx	W	Power down control
PWR_STATUS_BANKx	R	Power status
RETENTION_ENTER STATUS_BANKx	W, R	Data retention enable and status
SUPPLY_STATUS	R	PL power supply status
XRAM_FM_TZ_CTRL TZ_CTRL TZ_CTRL_LOCK	RW, SO	TrustZone control
PL_AXI[0:2]_CTRL/STATUS PL_AXI_LITE_CTRL/STATUS PS_AXI_CTRL/STATUS PS_APB_CTRL/STATUS	RW, R	Data port interfaces and programming interface isolation/reset control and status information
BANKx_AXI_CTRL/STATUS BANKx_APB_CTRL/STATUS	RW, R	Memory bank programming interface isolation/reset control and status information
Interrupt Registers
SLVERR BANK_PWR BANK_ECC BANK_RMW BANK_PWR_FSM INVALID_RET_REQ MULTIPLE_PWR_RET_REQ INT_XMPU INT_TIMEOUT INT_MISSION INT_PARITY	RW, R
xxx_ISR xxx_ITR	WTC W	Status and trigger registers
CE_xxx_IMR CE_xxx_IER CE_xxx_IDR	R W W	Correctable errors
UCE_xxx_IMR UCE_xxx_IER UCE_xxx_IDR	R W W	Uncorrectable errors

LPD_INT_CSR Register for AXI

The LPD AXI interface is controlled by the LPD_INT_CSR.LPD_AXI_XRAM register.

An AXI interface timeout interrupt is routed through the LPD_INT_CSR.TIMEOUT_xxx registers.

An AXI interface parity error interrupt is routed through the LPD_INT_CSR.PERR_xxx registers.

Protection Register Sets

Each memory bank includes a memory protection unit (XMPU). These protection units are described in the Memory Protection Units chapter. They are designed with 4 KB apertures.

Memory Bank Control Register Sets

Each memory bank includes an XRAM_CTRL register set to control the response of the controller to ECC errors and for reporting ECC errors, APB access errors, and powered-down access errors.

Table 2. Memory Bank Control Register Set
Register Name	Access Type	Description
ERR_CTRL	RW	Program response for APB programming errors and memory errors
APB_ISR APB_IMR APB_IER APB_IDR	WTC R W W	APB programming error interrupt registers
XRAM_ECC_CTRL	RW	Control ECC, single-bit correction, error injection
XRAM_CLR_EXE	W	Clear exclusive access monitors
XRAM_[CE,UE]_FFA	R	Address of first occurrence of correctable/uncorrectable error
XRAM_RMW_UE_FFA	R	Address of failed RMW access because of uncorrectable error
XRAM_[CE,UE]_FFD[0:3]	R	Failing data of first occurrence of correctable/uncorrectable error