XMPU Instances - XMPU Instances - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2026-03-06
Revision
1.9 English

PMC and PS Protection Units

The following table lists the XMPU instances.

Table 1. XMPU Instances in PMC and PS
Name Granularity Upstream Interface Downstream Interface Register Module Address
PMC_XMPU 4 KB PMC main switch PMC RAM and SBI 0xF12F_0000
OCM_XMPU 4 KB OCM switch OCM memory 0xFF98_0000
FPD_XMPU 4 KB FPD main switch APU GIC, FPD peripherals, and register modules 0xFD39_0000

DDRMC and Accelerator RAM Memory Protection Units

The following table lists the Accelerator RAM and DDRMC instances of the protection units. The Accelerator RAM memory has four XMPUs. Each DDR memory controller has one XMPU.

Table 2. DDRMC and Accelerator RAM Protection Units
Name Granularity Upstream Interfaces Downstream Interfaces Programming Interface
DDR Memory Controller (one per controller)

DDRMCx_XMPU

1 MB

Four-port NoC interface

DDR memory controller

NPI
Accelerator RAM (device option)

XRAM_XMPU0
XRAM_XMPU1
XRAM_XMPU2
XRAM_XMPU3

4 KB OCM switch Accelerator RAM APB