This section describes the key differences between the Versal adaptive SoC PMC and previous devices.
- The PMC system (replacement for the MPSoC's CSU and PMU) has its own dedicated power domain.
- Configuration frame interface (CFI) bus is dedicated to accessing the configuration frames and provides configuration and readback performance improvements. In conjunction with the network on chip (NoC), it replaces the internal configuration access ports (ICAP, PCAP, and MCAP) used in previous generations.
- NoC programming interface (NPI) provides register access for remote peripherals such as gigabit transceivers and DDR memory.
- Octal SPI boot mode supports compatible octal SPI flash memory with DDR mode providing a high-speed and low pin-count solution.
- SelectMAP boot mode loads PDI data and requires hardware flow control using the chip select (SMAP_CS_b) control signal with the SMAP_BUSY status signal. SMAP_CS_b must be controlled and must not be tied to GND. SMAP_CS_b must be asserted only when presenting PDI data. Otherwise, SMAP_CS_b must be deasserted before delivery of the first PDI word, within 24 SMAP_CLK cycles of an asserted SMAP_BUSY signal during PDI data delivery, after delivery of the last PDI data word, and whenever non-PDI data is presented. The SMAP_CLK registers PDI data from the SMAP_IO data pins and must run even when SMAP_CS_b is deasserted to clock logic related to the SMAP_BUSY status or related to internal forwarding of PDI data.
- Single TAP located in the platform management controller.
- Single DNA identification accessible via JTAG or in the AXI register set. The Versal device does not have a PL DNA or a corresponding PL DNA_PORT primitive.
- Internal configuration clock provides higher performance than prior generation.
- Debug packet controller (DPC) supports the high-speed debug port (HSDP) for processing packets from interfaces including HSDP Aurora and PCIe controllers.
- Integrated system monitor in the platform management controller.
- Enhanced encryption and decryption for increased resistance to differential power attacks (DPA).
- Two PUF outputs that are exclusively managed by the RCU, a unique readable device ID, and a unique device key encryption key (KEK) for encrypt/decrypt.
- Enhanced authenticated JTAG (RSA/ECDSA) access via JTAG.
- True random number generator (TRNG), additional AES user keys, and ECDSA authentication added for security applications.
- Connections from the gigabit transceivers, through the CPM and through LPD into the PMC configuration.
- The legacy quad SPI (LQSPI) controller mode is not supported in the Versal device.
- Execute-in-place (XIP) is not supported by Versal device boot modes.
- JTAG accessible internal private scan registers (with USER1-4 commands) are accessed with the PS9 primitive through the control, interface, and processing system (CIPS) IP. The Versal device does not have a BSCANE2 primitive.
- The soft error mitigation (XilSEM) library is a pre-configured and pre-verified solution to detect and optionally correct soft errors in the configuration memory of Versal devices.