Timer Register Set - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2025-07-28
Revision
1.8 English

The SWDT instances and register module base addresses are listed in the Watchdog Timer Instances section. The following table summarizes the SWDT registers.

Table 1. SWDT Timer Register Set
Register Name Offset Address Access Type Description
Common Registers
WProt , MWR 0x0000 RW Window registers write access control
Enable_and_Status , ESR 0x0004 R, RW, W1C Enables and interrupt status
Funct_Ctrl , FCR 0x0008 RW Function control


            IER
        

            IDR
        

            IMR
        

0x0030
0x0034
0x0038

W
W
R

 Interrupt enable, disable, and mask.
Window Timer Registers
First_Wind , FWR 0x000C RW First window count
Second_Wind , SWR 0x0010 RW Second window configuration
SST_Count , SSTWR 0x0014 RW Load the second sequence timer (SST) count value
Task_Sig0 , TSR0 0x0018 RW Task signature reg 0
Task_Sig1 , TSR1 0x001C RW Task signature reg 1
SST_Read , STR_WWDT 0x0020 R Read the current value of the second sequence timer (SST) up counter
Token_FB , TFR 0x0024 RW Token feedback
Token_Resp ,TRR 0x0028 RW Token response
Generic Timer Registers
G_Refresh , GWRR 0x1000 RW Generic watchdog refresh
G_CSR , GWCSR 0x2000 RW, R Generic watchdog control and status
G_Offset , GWOR 0x2008 RW Generic watchdog offset
G_Warm_Reset , GW_WR 0x2FD0 RW Generic watchdog warm reset