Test and debug are divided into the following chapters in Test and Debug:
Integrated Debug
The integrated debug resides in the PMC and includes the test access port (TAP) controller, the Arm® debug access port (DAP) controller, and the debug packet controller (DPC). The TAP controller supports PL configuration, ChipScope™ debug, and JTAG boundary-scan operations. The Arm DAP controller supports the Arm CoreSight™ debug and trace. The DPC is part of the high-speed debug port (HSDP) and allows access to all debug resources including Arm CoreSight debug and trace and ChipScope.
CoreSight Debug
The CoreSight debug environment is for software debug and transaction monitoring. It includes intrusive and non-intrusive interfaces into the processing system and programmable logic. The debug features provide heterogeneous software debug between the RPU, APU, and PL. CoreSight attaches to the debug hooks in the RPU and APU plus an interface to the PL for additional processors in a chip-wide heterogeneous system.