The TRM describes the overall hardware architecture of the device and the functional details of the processing system and the platform management controller (PMC).
The control and status registers for the processing system (PS) and PMC are described in the Versal Adaptive SoC Register Reference (AM012). For security-minded applications, see the Versal Adaptive SoC Security Register Reference Manual (AM018), which requires an active NDA to download from the Design Security Lounge.
The TRM is complemented by companion documents to provide detailed hardware functionality outside of the PS and the PMC. The outline of the TRM is described in this section.
Device and Document Overview
Introduction provides an introduction to the adaptive SoC.
The TRM technical content begins with Hardware Architecture. This is a hardware-centric section that covers the entire device. This section includes links to other parts of the TRM and to companion documents that include extensive technical information.
Platform Boot, Control and Status Functionality
The reset response, boot flow, and runtime services are provided by the PMC. The start-up activities of the PMC are described in Platform Boot, Control, and Status. The chapters in this section describe how the device comes up after a reset and how to manage the platform during normal device operation.
Address Maps and Package Signals
The TRM includes two reference sections for address maps, control register summaries, and tables that list the signals, interfaces, and pins. These sections include device-wide content.
PMC and Processing System Hardware
A major part of the TRM includes multiple technical reference sections that illustrate the detailed architectures and describe the functional models of each block in the PMC and processing system (PS).