The TTC control and status registers are accessed by an APB bus interface via the PMC local IOP interconnect. They are protected by the PMC XPPU protection unit. A TTC counter is controlled by one register set:
- TTC register module
The following table lists the TTC registers.
| Register | Access Type | Description |
|---|---|---|
| CLK_CTRLx | RW | Clock control for three counters |
| CNT_CTRLx | RW | Operational mode and reset for three counters |
| CNT_VALx | R | Current counter value for three counters |
| INTERVAL_CNTx | RW | Maximum count value for three counters |
| MATCHx_CNTx | RW | Match values for three counters; when count matches a value, then the interrupt bit is set. |
| ISR_CNTx | R | Interrupts status for interval, match, overflow, and event. |
| IER_CNTx | RW | Interrupts enable for interval, match, overflow, and event. |
| EVT_CTRL_TMRx | RW | Enable, pulse, and overflow. |
| EVT_CYCLE_TMRx | RW | APB interface clock cycle count for event. |