System-level Routes - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

Block Diagram

The supported interconnect datapaths between the PS/PL and the CPM are shown in the following figure.

Figure 1. CPM Transaction Route Block Diagram

PCIe Root Complex Mode

The transactions to and from the CPM are summarized in the following table for the PCIe® root complex mode. The direction of the transaction is reflected in the route name: source_destination. The PS designation includes everything that is not the CPM (for example, NoC/DDR).

Note: The root names that include an asterisk (*) include restrictions or programming notes.
Table 1. Transactions in PCIe Root Complex Mode
Route Name Source Via Destination Notes
Inbound from CPM
RC_IN 1 CPM_NOC0

CPM_PS switch,
SMMU/CCI, and
NoC interconnect

 DDR memory or PL Set the CCI_CFG_1 [0] bit = 1
RC_IN 2 CPM_NOC0

CPM_PS switch,
SMMU/CCI, and
FPD to OCM switch

 OCM memory  
RC_IN 3 CPM_NOC0

CPM_PS switch,
SMMU/CCI, and FPD switch

 FPD_AXI_PL interface  
RC_IN 4 CPM_NOC1 NoC interconnect DDR memory or PL Physical address
RC_IN 5 CPM_NOC0

CPM_PS switch

 Debug packet controller Physical address
Outbound To CPM
RC_OUT 1 APU

CCI and
PS_CPM switch

 CPM interconnect  
RC_OUT 2 PL NoC interconnect CPM interconnect  
RC_OUT 3 PL_AXI_FPD interface

SMMU TBU 5,
CCI, and
PS_CPM switch

 CPM interconnect  
RC_OUT 4 PL_AXILITE_FPD

SMMU TBU 2,
CCI, and
PS_CPM switch

 CPM interconnect  
RC_OUT 5 Debug packet controller PS_CPM switch CPM interconnect  

PCIe Endpoint Mode

The transactions to and from the CPM are summarized in the following table for the PCIe endpoint mode. The direction of the transaction is reflected in the source_destination route name. The PS designation includes everything that is not the CPM (for example, NoC/DDR).

Table 2. Transactions in PCIe Endpoint Mode
Route Name Source Via Destination Notes
From CPM To PS
EP_IN 1 CPM_NOC0

CPM_PS switch, and
NoC interconnect

 DDR memory or PL Physical address
EP_IN 2 CPM_NOC0

CPM_PS switch,
SMMU TBU 3
CCI,
FPD, and
OCM switch

 OCM memory  
EP_IN 3 CPM_NOC0

CPM_PS switch,
SMMU TBU 3,
CCI, and
FPD switch

 FPD_AXI_PL interface  
EP_IN 4 CPM_NOC1 NoC interconnect DDR memory or PL Physical address
EP_IN 5 CPM_NOC0 CPM_PS switch Debug packet controller  
From PS To CPM
EP_OUT 1 APU

CCI,
PS_CPM switch

 CPM interconnect  
EP_OUT 2 PL NoC interconnect CPM interconnect  
EP_OUT 3 PL_AXI_FPD interface

SMMU TBU 5,
CCI,
FPD switch, and
PS_CPM switch

 CPM interconnect  
EP_OUT 4 PL_AXILITE_FPD

SMMU TBU 2
CCI, and
PS_CPM switch

 CPM interconnect  
EP_OUT 5 Debug packet controller PS_CPM switch CPM interconnect